Logic Libraries

Updated On:2018-01-24
Gradation
Faraday IPs are rated according to the IPs’ maturity and customer acceptance. They are graded by the rules described as below,


Platinum P Five (5) productions verified
Gold G Mass production proven
Silver S Silicon proven, Formal release
Silver Minus S- Manufacturing onging
Bronze B Pre-Silicon release
 
Logic Libraries > PowerSlash Core Cell Library
> 12-Track 
Cell Name Descriptions Type Process Gradation Literature
FSH0L_GLS_POWERSLASH
_CORE
UMC 40nm LP/LVT Logic Process 12-track powerslash core cells Library_Group 40nm Bronze
FSH0L_GRS_POWERSLASH
_CORE
UMC 40nm LP/RVT LowK Logic Process 12-track Powerslash Cell Library Library_Group 40nm Bronze
 
Logic Libraries > PowerSlash Core Cell Library
> 12-Track > 12T HVT PSK Library 
Cell Name Descriptions Type Process Gradation Literature
FSH0L_HHS_POWERSLASH
_CORE
UMC 40nm LP/HVT Logic Process 12-Track High Speed Cell PowerSlash Library (C40) Library_Group 40nm Silver
 
 
Logic Libraries > PowerSlash Core Cell Library
> 12-Track > 12T LVT PSK Library 
Cell Name Descriptions Type Process Gradation Literature
FSH0L_HLS_POWERSLASH
_CORE
UMC 40nm LP/LVT Logic Process 12-Track High Speed Powerslash Core Cell Library Library_Group 40nm Silver
 
Logic Libraries > PowerSlash Core Cell Library
> 12-Track > 12T RVT PSK Library 
Cell Name Descriptions Type Process Gradation Literature
FSH0L_HRS_POWERSLASH
_CORE
UMC 40nm LP/RVT Logic Process 12-Track High Speed PowerSlash Cell Library (C40) Library_Group 40nm Silver