Dual-Port SRAM

Updated On:2018-01-23
Gradation
Faraday IPs are rated according to the IPs’ maturity and customer acceptance. They are graded by the rules described as below,


Platinum P Five (5) productions verified
Gold G Mass production proven
Silver S Silicon proven, Formal release
Silver Minus S- Manufacturing onging
Bronze B Pre-Silicon release
 
Memory Compiler > Dual-Port SRAM
> 8TSRAM > High Density DPSRAM, 8TSRAM 
Cell Name Descriptions Type Process Gradation Literature
FSH0L_A_SJ UMC 40nm LP Logic Process standard synchronous high density dual port SRAM memory compiler. Memory_IP 40nm Silver
FSH0L_A_SJRED UMC 40nm Logic Process standard synchronous high density dual port SRAM memory compiler with redundancy Memory_IP 40nm Silver
FSH0L_C_SJ 40LP High density dual port SRAM compiler with Vss booster feature Memory_IP 40nm Silver Minus
FSH0L_C_SJRED UMC 40nm LP Logic Process Dual-Port SRAM memory compiler with redundancy Memory_IP 40nm Silver Minus
FSH0L_T_SJ UMC 40nm Low Power Process Dual-Port SRAM compiler with dual power rail Memory_IP 40nm Bronze
 
Memory Compiler > Dual-Port SRAM
> 8TSRAM > High Density DPSRAM, 8TSRAM, Peri HVT, Power Gating 
Cell Name Descriptions Type Process Gradation Literature
FSH0L_L_SJHVTRED UMC 40NM Low-K Low Power synchronous Feature Dual Port SRAM memory compiler Memory_IP 40nm Contact Sales
 
 
Memory Compiler > Dual-Port SRAM
> 8TSRAM > High Density DPSRAM, 8TSRAM, Peri LVT 
Cell Name Descriptions Type Process Gradation Literature
FSH0L_A_SJLVT UMC 40nm LP Logic Process standard synchronous high density dual port SRAM memory compiler with LVT Memory_IP 40nm Silver
FSH0L_A_SJREDLVT UMC 40nm LP Logic Process standard synchronous high density dual port SRAM memory compiler with ROW redundancy with LVt peripheral Memory_IP 40nm Silver
FSH0L_C_SJLVT UMC 40nm LP Logic Process Dual-Port SRAM Memory Compiler with LVT peripheral Memory_IP 40nm Silver Minus
FSH0L_C_SJLVTRED UMC 40nm LP Logic Process Dual-Port SRAM memory compiler with redundancy and LVT peripheral Memory_IP 40nm Silver Minus
 
Memory Compiler > Dual-Port SRAM
> 8TSRAM > High Density DPSRAM, 8TSRAM, Peri LVT, Power Gating 
Cell Name Descriptions Type Process Gradation Literature
FSH0L_L_SJLVT UMC 40nm LP LowK Logic Process ULL Dual-Port SRAM Memory Compiler with Peri-LVT Memory_IP 40nm Silver Minus
FSH0L_L_SJLVTRED UMC 40NM Low-K Low Power synchronous Feature Dual Port SRAM memory compiler Memory_IP 40nm Bronze
 
Memory Compiler > Dual-Port SRAM
> 8TSRAM > High Density DPSRAM, 8TSRAM, Power Gating 
Cell Name Descriptions Type Process Gradation Literature
FSH0L_L_SJ UMC 40nm LP Dual Port SRAM compiler with Sleep/Retention mode Memory_IP 40nm Silver Minus
FSH0L_L_SJRED UMC 40nm Low-K Low Power synchronous Feature Dual Port SRAM memory compiler Memory_IP 40nm Silver Minus