Memory Compiler

Updated On:2018-04-23
Gradation
Faraday IPs are rated according to the IPs’ maturity and customer acceptance. They are graded by the rules described as below,


Platinum P Five (5) productions verified
Gold G Mass production proven
Silver S Silicon proven, Formal release
Silver Minus S- Manufacturing onging
Bronze B Pre-Silicon release
 
Memory Compiler > ROM
> VIA1 ROM > VIA1 ROM 
Cell Name Descriptions Type Process Gradation Literature
FSH0L_A_SP UMC 40 LP/RVT LowK Logic Process Via1 ROM Memory Compiler Memory_IP 40nm Silver
FSH0L_B_SP UMC 40nm LP Logic Process Via ROM compiler with WL booster Memory_IP 40nm Silver
 
Memory Compiler > ROM
> VIA1 ROM > VIA1 ROM, Peri HVT 
Cell Name Descriptions Type Process Gradation Literature
FSH0U_A_SPHVT UMC 40nm ultra low power via1 ROM complier Memory_IP 40nm Bronze
FSH0U_L_SPHVT UMC 40nm uLP process ULL Via1 ROM compiler Memory_IP 40nm Bronze
 
Memory Compiler > ROM
> VIA1 ROM > VIA1 ROM, Peri LVT 
Cell Name Descriptions Type Process Gradation Literature
FSH0L_B_SPLVT UMC 40nm LP Logic Process Via ROM compiler with peri LVT and WL booster Memory_IP 40nm Silver
 
Memory Compiler > ROM
> VIA1 ROM > VIA1 ROM, Sleep Mode 
Cell Name Descriptions Type Process Gradation Literature
FSH0L_L_SP UMC 40LP Via1 ROM compiler with Sleep mode Memory_IP 40nm Silver
 
Memory Compiler > ROM
> VIA1 ROM > VIA1 ROM, Sleep Mode, Peri LVT 
Cell Name Descriptions Type Process Gradation Literature
FSH0L_L_SPLVT UMC 40LP via1 ROM compiler with Sleep mode & peri LVT Memory_IP 40nm Silver