Memory Compiler

Updated On:2018-01-23
Gradation
Faraday IPs are rated according to the IPs’ maturity and customer acceptance. They are graded by the rules described as below,


Platinum P Five (5) productions verified
Gold G Mass production proven
Silver S Silicon proven, Formal release
Silver Minus S- Manufacturing onging
Bronze B Pre-Silicon release
 
Memory Compiler > 1-Port SRAM
> 6TSRAM > High Density & Low Power 1PSRAM, 6TSRAM 
Cell Name Descriptions Type Process Gradation Literature
FSH0L_L_SH ULL Single Port SRAM ,UMC 40nm LP process. Memory_IP 40nm Silver
FSH0L_L_SHRED ULL Single Port SRAM with row redundancy , UMC 40nm LP Process. Memory_IP 40nm Silver Minus
FSH0U_B_SH UMC 40nm Low K Ultra Low Power Logic Process High-Density Single Port SRAM Compiler Memory_IP 40nm Contact Sales
 
 
Memory Compiler > 1-Port SRAM
> 6TSRAM > High Density & Low Power 1PSRAM, 6TSRAM, Peri HVT 
Cell Name Descriptions Type Process Gradation Literature
FSH0L_L_SHHVT ULL Single Port SRAM with peri HVT, UMC 40nm LP process. Memory_IP 40nm Bronze
FSH0L_L_SHHVTRED ULL Sigle Port SRAM with HVT Row redundancy, UMC 40nm LP process. Memory_IP 40nm Silver Minus
FSH0L_L_SHLVT UMC 40nm LP/LVT SP-SRAM compiler with peri-LVT and Power gating Memory_IP 40nm Bronze
FSH0L_L_SHLVTRED UMC 40nm LP/LVT SP-SRAM compiler with power gating & row redundancy Memory_IP 40nm Bronze
 
Memory Compiler > 1-Port SRAM
> 6TSRAM > High Density & Ultra Low Power 1PSRAM, 6TSRAM 
Cell Name Descriptions Type Process Gradation Literature
FSH0U_B_SHHVT UMC 40nm Low K Ultra Low Power Logic Process High-Density Single Port SRAM Compiler Memory_IP 40nm Contact Sales
 
FSH0U_B_SHRED UMC 40nm Low K Ultra Low Power Logic Process High-Density Single Port SRAM Compiler Memory_IP 40nm Contact Sales
 
 
Memory Compiler > 1-Port SRAM
> 6TSRAM > High Density 1PSRAM, 6TSRAM 
Cell Name Descriptions Type Process Gradation Literature
FSH0L_B_SH UMC 40nm LP/HVT Logic Process with 6TSRAM (0.242 mm2) One Port SRAM Memory Compiler Memory_IP 40nm Silver
FSH0L_B_SHRED UMC 40nm LP Logic Process Single Port SRAM memory compiler with row redundancy Memory_IP 40nm Silver
FSH0L_D_SH UMC 40nm Low Power Process SP-SRAM with 213 bit cell Memory_IP 40nm Silver Minus
FSH0L_D_SHRED UMC 40nm Low Power Process SP-SRAM memory compiler with row redundancy and 213 bit cell Memory_IP 40nm Bronze
FSH0L_H_SH UMC 40nm Low Power Process Single-Port SRAM 213cell with power gating Memory_IP 40nm Silver Minus
FSH0L_H_SHRED UMC 40nm Low Power Process PG SP-SRAM with Row redundancy for 213 bit cell Memory_IP 40nm Bronze
FSH0L_K_SH UMC 40nm Low Power Process Single-Port SRAM for dual power rail Memory_IP 40nm Bronze
FSH0L_L_SYHVT UMC 40nm LP with power gating & peri-HVT 1PRF Memory_IP 40nm Contact Sales
 
FSH0U_L_SYHVT UMC 40nm uLP process ULL One Port Register File memory compiler Memory_IP 40nm Bronze
 
Memory Compiler > 1-Port SRAM
> 6TSRAM > High Density 1PSRAM, 6TSRAM, Peri HVT 
Cell Name Descriptions Type Process Gradation Literature
FSH0L_D_SHHVT UMC 40nm LP Logic Process Single Port SRAM memory compiler using 213 bit -cell with peri-HVT Memory_IP 40nm Silver Minus
FSH0L_H_SHHVT UMC 40nm LP Logic Process ULL Single Port SRAM Memory Compiler using 213 bit-cell with peri-HVT Memory_IP 40nm Silver Minus
FSH0U_B_SHHVTRED UMC 40nm Low K Ultra Low Power Logic Process High-Density Single Port SRAM Compiler Memory_IP 40nm Contact Sales
 
FSH0U_L_SHHVT UMC 40nm uLP process ULL Single-Port SRAM Memory_IP 40nm Contact Sales
 
 
Memory Compiler > 1-Port SRAM
> 6TSRAM > High Density 1PSRAM, 6TSRAM, Peri LVT 
Cell Name Descriptions Type Process Gradation Literature
FSH0L_A_SEREDLVT UMC 40nm LP Logic Process Ultra High-Speed Single Port SRAM Memory compiler with Redundancy Memory_IP 40nm Silver Minus
FSH0L_B_SHLVT UMC 40nm LP Logic Process Single Port SRAM Compiler with LVT Periphery Memory_IP 40nm Silver
FSH0L_B_SHREDLVT UMC 40nm LP Logic Process Single Port SRAM Compiler LVT with row redundancy Memory_IP 40nm Silver
FSH0L_D_SHLVT UMC 40nm LP Logic Process Single Port SRAM Memory Compiler using 213 bit-cell with Peri-LVT Memory_IP 40nm Silver Minus
FSH0L_D_SHLVTRED UMC 40nm LP process synchronous high density (0.213LPHVT cell) single port SRAM compiler with row redundancy. Memory_IP 40nm Bronze
FSH0L_G_SELVT UMC 40um LP Logic Process High Speed Singl Port SRAM Compiler with 303RVT cell and Peri LVT Memory_IP 40nm Silver
FSH0L_H_SHLVT UMC 40nm LP Logic Process ULL Single Port SRAM Memory Compiler using 213 bit-cell with peri-LVT Memory_IP 40nm Silver Minus
FSH0L_H_SHLVTRED 40LP PG SP-SRAM LVT Peripheral with Row redundancy for 213 cell Memory_IP 40nm Bronze
 
Memory Compiler > 1-Port SRAM
> 6TSRAM > Ultra High Speed 1PSRAM, 6TSRAM, Peri LVT 
Cell Name Descriptions Type Process Gradation Literature
FSH0L_A_SELVT UMC 40LP 303HVT cell /Peri-LVT Memory_IP 40nm Silver Minus