Memory Compiler

Updated On:2018-06-23
Gradation
Faraday IPs are rated according to the IPs’ maturity and customer acceptance. They are graded by the rules described as below,


Platinum P Five (5) productions verified
Gold G Mass production proven
Silver S Silicon proven, Formal release
Silver Minus S- Manufacturing onging
Bronze B Pre-Silicon release
 
Memory Compiler > 1-Port SRAM
> 6TSRAM > High Density & Low Power 1PSRAM, 6TSRAM, Peri HVT 
Cell Name Descriptions Type Process Gradation Literature
FSH0L_L_SHHVT ULL Single Port SRAM with peri HVT, UMC 40nm LP process. Memory_IP 40nm Bronze
FSH0L_L_SHHVTRED ULL Sigle Port SRAM with HVT Row redundancy, UMC 40nm LP process. Memory_IP 40nm Silver Minus
FSH0L_L_SHLVT UMC 40nm LP/LVT SP-SRAM compiler with peri-LVT and Power gating Memory_IP 40nm Bronze
FSH0L_L_SHLVTRED UMC 40nm LP/LVT SP-SRAM compiler with power gating & row redundancy Memory_IP 40nm Bronze