Memory Compiler

Updated On:2018-06-23
Gradation
Faraday IPs are rated according to the IPs’ maturity and customer acceptance. They are graded by the rules described as below,


Platinum P Five (5) productions verified
Gold G Mass production proven
Silver S Silicon proven, Formal release
Silver Minus S- Manufacturing onging
Bronze B Pre-Silicon release
 
Memory Compiler > 1-Port SRAM
> 6TSRAM > High Density 1PSRAM, 6TSRAM 
Cell Name Descriptions Type Process Gradation Literature
FSH0L_B_SH UMC 40nm LP/HVT Logic Process with 6TSRAM (0.242 mm2) One Port SRAM Memory Compiler Memory_IP 40nm Silver
FSH0L_B_SHRED UMC 40nm LP Logic Process Single Port SRAM memory compiler with row redundancy Memory_IP 40nm Silver
FSH0L_D_SH UMC 40nm Low Power Process SP-SRAM with 213 bit cell Memory_IP 40nm Silver Minus
FSH0L_D_SHRED UMC 40nm Low Power Process SP-SRAM memory compiler with row redundancy and 213 bit cell Memory_IP 40nm Bronze
FSH0L_H_SH UMC 40nm Low Power Process Single-Port SRAM 213cell with power gating Memory_IP 40nm Silver Minus
FSH0L_H_SHRED UMC 40nm Low Power Process PG SP-SRAM with Row redundancy for 213 bit cell Memory_IP 40nm Bronze
FSH0L_K_SH UMC 40nm Low Power Process Single-Port SRAM for dual power rail Memory_IP 40nm Bronze
FSH0L_L_SYHVT UMC 40nm LP with power gating & peri-HVT 1PRF Memory_IP 40nm Contact Sales
 
FSH0U_L_SYHVT UMC 40nm uLP process ULL One Port Register File memory compiler Memory_IP 40nm Bronze