Memory Compiler

Updated On:2018-01-23
Gradation
Faraday IPs are rated according to the IPs’ maturity and customer acceptance. They are graded by the rules described as below,


Platinum P Five (5) productions verified
Gold G Mass production proven
Silver S Silicon proven, Formal release
Silver Minus S- Manufacturing onging
Bronze B Pre-Silicon release
 
Memory Compiler > 1-Port SRAM
> 6TSRAM > High Density 1PSRAM, 6TSRAM, Peri HVT 
Cell Name Descriptions Type Process Gradation Literature
FSH0L_D_SHHVT UMC 40nm LP Logic Process Single Port SRAM memory compiler using 213 bit -cell with peri-HVT Memory_IP 40nm Silver Minus
FSH0L_H_SHHVT UMC 40nm LP Logic Process ULL Single Port SRAM Memory Compiler using 213 bit-cell with peri-HVT Memory_IP 40nm Silver Minus
FSH0U_B_SHHVTRED UMC 40nm Low K Ultra Low Power Logic Process High-Density Single Port SRAM Compiler Memory_IP 40nm Contact Sales
 
FSH0U_L_SHHVT UMC 40nm uLP process ULL Single-Port SRAM Memory_IP 40nm Contact Sales