Memory Compiler

Updated On:2018-01-23
Gradation
Faraday IPs are rated according to the IPs’ maturity and customer acceptance. They are graded by the rules described as below,


Platinum P Five (5) productions verified
Gold G Mass production proven
Silver S Silicon proven, Formal release
Silver Minus S- Manufacturing onging
Bronze B Pre-Silicon release
 
Memory Compiler > 2-Port Register File
> 8TSRAM > High Density 2PRF, 8TSRAM 
Cell Name Descriptions Type Process Gradation Literature
FSH0L_A_SZ UMC 40nm LP/RVT LowK Logic 2-Port Register File Memory Compiler Memory_IP 40nm Silver
FSH0L_B_SZ UMC 40nm LP/Low-K process ; Two Port Register File memory compiler Memory_IP 40nm Silver
FSH0L_L_SZ 40LP 2PRF with Sleep/Retention/Nap mode feature Memory_IP 40nm Silver Minus
 
Memory Compiler > 2-Port Register File
> 8TSRAM > High Density 2PRF, 8TSRAM, Dual Power Rail 
Cell Name Descriptions Type Process Gradation Literature
FSH0L_T_SZ UMC 40nm Low Power Process , Two Port Register File with dual power rail Memory_IP 40nm Contact Sales
 
Memory Compiler > 2-Port Register File
> 8TSRAM > High Density 2PRF, 8TSRAM, Peri HVT 
Cell Name Descriptions Type Process Gradation Literature
FSH0L_L_SZHVT UMC 40nm Logic process standard Synchronous High Density Two Port Register File SRAM memory compiler. Memory_IP 40nm Contact Sales
 
Memory Compiler > 2-Port Register File
> 8TSRAM > High Density 2PRF, 8TSRAM, Peri LVT 
Cell Name Descriptions Type Process Gradation Literature
FSH0L_A_SZLVT UMC 40nm LP Logic Process Two-Port Register File with LVT Peripheral Memory Compiler Memory_IP 40nm Contact Sales
 
FSH0L_B_SZLVT UMC 40nm LP/LVT Process; Two Port Register File with LVT Memory_IP 40nm Silver
FSH0L_L_SZLVT 40LP 2PRF with Sleep/Retention/Nap mode & peri LVT feature Memory_IP 40nm Silver Minus