Memory Compiler

Updated On:2018-01-20
Gradation
Faraday IPs are rated according to the IPs’ maturity and customer acceptance. They are graded by the rules described as below,


Platinum P Five (5) productions verified
Gold G Mass production proven
Silver S Silicon proven, Formal release
Silver Minus S- Manufacturing onging
Bronze B Pre-Silicon release
 
Memory Compiler > Dual-Port SRAM
> 8TSRAM > High Density DPSRAM, 8TSRAM 
Cell Name Descriptions Type Process Gradation Literature
FSH0L_A_SJ UMC 40nm LP Logic Process standard synchronous high density dual port SRAM memory compiler. Memory_IP 40nm Silver
FSH0L_A_SJRED UMC 40nm Logic Process standard synchronous high density dual port SRAM memory compiler with redundancy Memory_IP 40nm Silver
FSH0L_C_SJ 40LP High density dual port SRAM compiler with Vss booster feature Memory_IP 40nm Silver Minus
FSH0L_C_SJRED UMC 40nm LP Logic Process Dual-Port SRAM memory compiler with redundancy Memory_IP 40nm Silver Minus
FSH0L_T_SJ UMC 40nm Low Power Process Dual-Port SRAM compiler with dual power rail Memory_IP 40nm Bronze