Memory Compiler

Updated On:2018-01-21
Gradation
Faraday IPs are rated according to the IPs’ maturity and customer acceptance. They are graded by the rules described as below,


Platinum P Five (5) productions verified
Gold G Mass production proven
Silver S Silicon proven, Formal release
Silver Minus S- Manufacturing onging
Bronze B Pre-Silicon release
 
Memory Compiler > Dual-Port SRAM
> 8TSRAM > High Density DPSRAM, 8TSRAM, Peri LVT 
Cell Name Descriptions Type Process Gradation Literature
FSH0L_A_SJLVT UMC 40nm LP Logic Process standard synchronous high density dual port SRAM memory compiler with LVT Memory_IP 40nm Silver
FSH0L_A_SJREDLVT UMC 40nm LP Logic Process standard synchronous high density dual port SRAM memory compiler with ROW redundancy with LVt peripheral Memory_IP 40nm Silver
FSH0L_C_SJLVT UMC 40nm LP Logic Process Dual-Port SRAM Memory Compiler with LVT peripheral Memory_IP 40nm Silver Minus
FSH0L_C_SJLVTRED UMC 40nm LP Logic Process Dual-Port SRAM memory compiler with redundancy and LVT peripheral Memory_IP 40nm Silver Minus