Interface Solution

Updated On:2018-06-21
Gradation
Faraday IPs are rated according to the IPs’ maturity and customer acceptance. They are graded by the rules described as below,


Platinum P Five (5) productions verified
Gold G Mass production proven
Silver S Silicon proven, Formal release
Silver Minus S- Manufacturing onging
Bronze B Pre-Silicon release
 
Interface Solution > DDR
> DDR PHY - Data Block > DDR3/3L - Data Block 
Cell Name Descriptions Type Process Gradation Literature
FXDDR3D100HH0L DDR23 COMBO PHY Data Block ; UMC 40nm LP/RVT LowK Logic Process with 2.5V device Analog_IP 40nm Silver
FXDDR3D502HH0L Data Block of DDR3/DDR3L/DDR2/LPDDR2/LPDDR Combo PHY for Chip Application (compliant with DFI spec); UMC 40nm LP LowK Logic Process Analog_IP 40nm Silver Minus
FXDDR3DFC502HH0L DDR3 Combo PHY Data Block for solder bump application; UMC 40nm LP/RVT Logic Process Analog_IP 40nm Contact Sales
 
FXDDR3LTD102HH0L DDR3/DDR3L/LPDDR2 combo PHY ( not support DDR3 leveling function), data block;UMC 40nm LP/RVT LowK Logic Process . Analog_IP 40nm Contact Sales
 
 
Interface Solution > DDR
> DDR PHY - Data Block > DDR4 - Data Block 
Cell Name Descriptions Type Process Gradation Literature
FXDDR4D16FC101HH0L 40nm LP DDR3/4 LPDDR23 COMBO PHY DATA Block for Flip Chip usage Analog_IP 40nm Contact Sales
 
FXDDR4DFD612HH0L Data Block of DDR3/DDR4/LPDDR2/LPDDR3 Combo PHY for copper pillar bump Flip chip version ; UMC 40nm LP LowK Logic Process Analog_IP 40nm Contact Sales
 
Interface Solution > DDR
> DDR PHY - Data Block > DDR4 PHY - Data Block 
Cell Name Descriptions Type Process Gradation Literature
FXDDR4D16FC602HH0L Data Block of DDR3/DDR4/LPDDR2/LPDDR3 Combo PHY for Solder bump Flip chip version ; UMC 40nm LP LowK Logic Process Analog_IP 40nm Contact Sales
 
 
Interface Solution > DDR
> DDR PHY - Data Block > LPDDR2 - Data Block 
Cell Name Descriptions Type Process Gradation Literature
FXLPDDR2D102HH0L_SIP 40nm LPDDR2-PHY data block for SIP Analog_IP 40nm Contact Sales
 
 
Interface Solution > DDR
> DDR PHY - Data Block > LPDDR3 - Data Block 
Cell Name Descriptions Type Process Gradation Literature
FXLPDDR3D16W101HH0L 40nm LPDDR3-PHY Data block for LightCo ; UMC 40nm LP/LVT Logic Process Analog_IP 40nm Contact Sales