Interface Solution

Updated On:2018-01-20
Gradation
Faraday IPs are rated according to the IPs’ maturity and customer acceptance. They are graded by the rules described as below,


Platinum P Five (5) productions verified
Gold G Mass production proven
Silver S Silicon proven, Formal release
Silver Minus S- Manufacturing onging
Bronze B Pre-Silicon release
 
Interface Solution > DDR
> DDR PHY - Command/Address > DDR3/3L - Command/Address 
Cell Name Descriptions Type Process Gradation Literature
FXDDR3A100HH0L DDR23 COMBO PHY CMD/ADDR BLOCK ; UMC 40LP/RVT LowK Logic Process with 2.5V device Analog_IP 40nm Silver
FXDDR3A502HH0L Command/Address Block of DDR3/DDR3L/DDR2/LPDDR2/LPDDR Combo PHY for Chip Application (compliant with DFI spec); UMC 40nm LP LowK Logic Process Analog_IP 40nm Silver
FXDDR3A503HH0L DDR3 Combo PHY COMM/ADDR Block for 2-rank and solder bump application; UMC 40nm LP/RVT Logic Process Analog_IP 40nm Contact Sales
 
FXDDR3AFC502HH0L DDR3 Combo PHY COMM/ADDR Block for 2-rank and solder bump application; UMC 40nm LP/RVT Logic Process Analog_IP 40nm Contact Sales