Analog

Updated On:2018-01-21
Gradation
Faraday IPs are rated according to the IPs’ maturity and customer acceptance. They are graded by the rules described as below,


Platinum P Five (5) productions verified
Gold G Mass production proven
Silver S Silicon proven, Formal release
Silver Minus S- Manufacturing onging
Bronze B Pre-Silicon release
 
Analog > Clock
> PLL > 20M ~ 500M, Generic PLL 
Cell Name Descriptions Type Process Gradation Literature
FXPLL010HH0L Input 10-50M Hz, output 10-200M Hz, frequency synthesizable PLL; UMC 40nm LP/RVT Logic Process Analog_IP 40nm Silver
FXPLL010HH0L_FTC Input 10-50M Hz, output 10-200M Hz, frequency synthesizable PLL; UMC 40nm LP/RVT Logic Process(Note:same schematic with FXPLL010HH0L, but Poly Density Errors are waived in layout for 40% area reduced.) Analog_IP 40nm Bronze
FXPLL125HH0L Input 12M Hz, output clock1 540M Hz and output clock2 120M Hz, PLL; UMC 40nm LP/RVT Low-K Logic Process Analog_IP 40nm Silver Minus
FXPLL134HH0L miniPLL (TM) Phase-Locked Loop (PLL) with an operating frequency range of between 250 MHz and 500 MHz ; UMC 40nm LP/RVT Logic Process Analog_IP 40nm Bronze
FXPLL360HH0L_LTE2 Input 25M~440MHz, output 267M-533M, 200M-400M and 160M-320M, frequency synthesizable PLL; UMC 40nm LP/RVT Logic Process Analog_IP 40nm Contact Sales
 
FXPLL362HH0L Input 200MHz - 400MHz, output clock_1X 200MHz - 400MHz, output clock_2X 400MHz - 800MHz, output clock_4X 800MHz-1600MHz,frequency synthesizable PLL;UMC 40nm LP/RVT LowK Logic process Analog_IP 40nm Silver Minus