Analog

Updated On:2018-04-25
Gradation
Faraday IPs are rated according to the IPs’ maturity and customer acceptance. They are graded by the rules described as below,


Platinum P Five (5) productions verified
Gold G Mass production proven
Silver S Silicon proven, Formal release
Silver Minus S- Manufacturing onging
Bronze B Pre-Silicon release
 
Analog > Clock
> PLL > 500M ~ 1G, Generic PLL 
Cell Name Descriptions Type Process Gradation Literature
FXPLL360HH0L Input 25M-66M Hz, output 400M-800M Hz, frequency synthesizable PLL; UMC 40nm LP/RVT Logic Process Analog_IP 40nm Silver
FXPLL510HH0L_DPHY Input 6M-27M Hz, output 10M-850M Hz, frequency synthesizable PLL; UMC 40nm Logic LP RVT and LVT process Analog_IP 40nm Silver
FXPLLLV362HH0L This IP for DDR4, Input 200MHz - 800MHz, output clock_1X 200MHz - 800MHz, output clock_2X 400MHz - 1600MHz, output,frequency synthesizable PLL; UMC 40nm LP Logic Process Analog_IP 40nm Contact Sales