Analog |
Updated On:2018-04-27 |
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Analog > Clock |
> PLL > over 1G, Generic PLL |
Cell Name |
Descriptions |
Type |
Process |
Gradation |
Literature |
FXPLL110HH0L
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Input 10M-200M Hz, output 62.5M-1G Hz, frequency synthesizable PLL; UMC 40 nm LP/RVT Low-K Logic Process |
Analog_IP |
40nm |
Silver
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FXPLL120HH0L
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Input 20M-200M Hz, output 500M-1G Hz, frequency synthesizable PLL; UMC 40nm LP/RVT LowK Logic Process |
Analog_IP |
40nm |
Silver
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