Interface Solution

Updated On:2018-06-23
Gradation
Faraday IPs are rated according to the IPs’ maturity and customer acceptance. They are graded by the rules described as below,


Platinum P Five (5) productions verified
Gold G Mass production proven
Silver S Silicon proven, Formal release
Silver Minus S- Manufacturing onging
Bronze B Pre-Silicon release
 
Interface Solution > LVDS
> FPD LVDS BIAS Circuit 
Cell Name Descriptions Type Process Gradation Literature
FXLVBGR030HH0L 10 lane FXSLVTX030HH0L bias circuit ; UMC 40nm LP/RVT Logic Process Analog_IP 40nm Silver