Interface Solution

Updated On:2018-04-25
Gradation
Faraday IPs are rated according to the IPs’ maturity and customer acceptance. They are graded by the rules described as below,


Platinum P Five (5) productions verified
Gold G Mass production proven
Silver S Silicon proven, Formal release
Silver Minus S- Manufacturing onging
Bronze B Pre-Silicon release
 
Interface Solution > LVDS
> FPD LVDS Receiver 
Cell Name Descriptions Type Process Gradation Literature
FXLVDSRX060HH0L LVDS RX,UMC 40nm LP/RVT LowK Logic Process Analog_IP 40nm Silver
FXLVDSRX080HH0L LVDS RX IO PAD 500 Mbps ,UMC 40nm LP/RVT LowK Logic Process Analog_IP 40nm Contact Sales
 
FXLVDSRX080HH0L_BUMP LVDS RX IO PAD 500 Mbps, UMC 40nm LP/RVT LowK Logic Process, Bump pad. Analog_IP 40nm Contact Sales
 
FXLVIORX800HH0L 1.8v LVDS RX IO 800Mbps, UMC 40nm LP/RVT LowK Logic Process Analog_IP 40nm Contact Sales
FXLVRX020HH0L 3.3v LVDS RX,UMC 40nm LP/RVT LowK Logic Process Analog_IP 40nm Contact Sales
 
FXLVRX030HH0L 3.3v LVDS RX, 3 data lane and 1 clock lane using UMC 40nm LP/RVT LowK Logic Process Analog_IP 40nm Bronze
FXLVRX038HH0L 8 Lanes LVDS RX IO PAD, UMC 40nm LP/RVT LowK Logic Process Analog_IP 40nm Contact Sales
 
FXLVRX050HH0L 3.3v LVDS RX IO 1.25Gbps, UMC 40nm LP/RVT LowK Logic Process Analog_IP 40nm Contact Sales
 
FXLVRX080HH0L LVDS RX IO PAD 500 Mbps, UMC 40nm LP/RVT LowK Logic Process, for flip chip Analog_IP 40nm Contact Sales
 
FXLVRX5308HH0L 5-Data Channel DLL-based LVDS RX ; 40LP/RVT low-K process ; 3.3V IO / 1.1V Core ; Clock Range 16Mhz~120Mhz Analog_IP 40nm Contact Sales
FXLVRXBS050HH0L The bias block only for FXLVRX050HH0L, UMC 40nm LP/RVT LowK Logic Process Analog_IP 40nm Contact Sales
 
FXLVRXBS080HH0L The bias block only for FXLVDSRX080HH0L, UMC 40nm LP/RVT LowK Logic Process Analog_IP 40nm Contact Sales