Memory Compiler |
Updated On:2018-04-25 |
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Memory Compiler > 1-Port Register File |
> 6TSRAM > High Density 1PRF, 6TSRAM, Peri HVT, Power Gating |
Cell Name |
Descriptions |
Type |
Process |
Gradation |
Literature |
FSH0U_A_SYHVT
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UMC 40nm uLP Logic Process 1-Port Register File with Peri-HVT |
Memory_IP |
40nm |
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