Interface Solution

Updated On:2018-04-27
Gradation
Faraday IPs are rated according to the IPs’ maturity and customer acceptance. They are graded by the rules described as below,


Platinum P Five (5) productions verified
Gold G Mass production proven
Silver S Silicon proven, Formal release
Silver Minus S- Manufacturing onging
Bronze B Pre-Silicon release
 
Interface Solution > DDR
> DDR IO > DDR2 - SSTL18 IO Library 
Cell Name Descriptions Type Process Gradation Literature
FOF0L_PRS25_TMVH25L1
8_SSTL2WPWL_IO
55LP DDR1/DDR2 IO. 1. U55 LP Process 2. DDR2/DDR1 IO -2.5V SSTL2/1.8 SSTl18 ( CMOS/SSTL) –4 Driving strength @ Target: DDR 533 Mbps( IO 266 MHz) -VCCK Core power-off, All IO pull low Library_Group 55nm Bronze
 
Interface Solution > DDR
> DDR PHY - Command/Address > DDR1 - Command/Address 
Cell Name Descriptions Type Process Gradation Literature
FXDDR1A173HF0A DDR1/MDDR PHY CMD/ADDR BLOCK ; UMC 55nm SP/RVT with 2.5V device LowK Logic Process Analog_IP 55nm Bronze
 
 
Interface Solution > DDR
> DDR PHY - Command/Address > DDR2 - Command/Address 
Cell Name Descriptions Type Process Gradation Literature
FXDDR2A173HF0A DDR2/MDDR Combo PHY CMD ADDR block ; UMC 55nm SP/RVT Lowk Process with 2.5V device Analog_IP 55nm Silver
FXDDR2A174HF0A DDR2/MDDR PHY CMD/ADDR BLOCK for DIMM usage; UMC 55nm 1.0V with 2.5V device SP/RVT LowK Logic Process Analog_IP 55nm Silver
 
Interface Solution > DDR
> DDR PHY - Command/Address > DDR3/3L - Command/Address 
Cell Name Descriptions Type Process Gradation Literature
FXDDR3A300HF0A Command/Address Block of DDR3 Combo PHY for DIMM version ; UMC 55nm SP/RVT LowK Logic Process Analog_IP 55nm Silver
FXDDR3A300HF0L Command/Address Block of DDR3 Combo PHY for DIMM version ; UMC 55nm LP/RVT LowK Logic Process Analog_IP 55nm Silver Minus
FXDDR3A402HF0A Command/Address Block of DDR3/DDR3L/DDR2/LPDDR2/LPDDR Combo PHY for Chip Application; UMC 55nm SP/RVT LowK Logic Process Analog_IP 55nm Silver
FXDDR3A403HF0A Command/Address Block of DDR3/DDR3L/DDR2/LPDDR2/LPDDR Combo PHY for Chip Application;UMC 55nm SP/RVT LowK PROCESS. Analog_IP 55nm Silver
FXDDR3A412HF0L Command/Address Block of DDR3/DDR3L/DDR2/LPDDR2/LPDDR Combo PHY for Chip Application; UMC 55nm LP/RVT LowK Logic Process Analog_IP 55nm Bronze
FXDDR3A502HF0A Command/Address Block of DDR3/DDR3L/DDR2/LPDDR2/LPDDR Combo PHY for Chip Application (compliant to DFI); UMC 55nm SP/RVT LowK Logic Process Analog_IP 55nm Contact Sales
 
 
Interface Solution > DDR
> DDR PHY - Command/Address > LPDDR2 - Command/Address 
Cell Name Descriptions Type Process Gradation Literature
FXDDR3A412HF0A Command/Address Block of DDR3/DDR3L/DDR2/LPDDR2/LPDDR Combo PHY for Chip Application; UMC 55nm SP/RVT LowK Logic Process Analog_IP 55nm Bronze
 
Interface Solution > DDR
> DDR PHY - Compensation > DDR2 - Compensation 
Cell Name Descriptions Type Process Gradation Literature
FXDDR2COMP010HF0A DDR2 PHY Compensation block; UMC 55nm SP/RVT LowK Logic Process Analog_IP 55nm Silver
FXDDR2COMP010HF0A DDR2 PHY Compensation block; UMC 55nm SP/RVT LowK Logic Process Analog_IP 55nm Silver
 
Interface Solution > DDR
> DDR PHY - Compensation > DDR3/3L - Compensation 
Cell Name Descriptions Type Process Gradation Literature
FXDDR3COMP300HF0A Compensation Block of DDR3 Combo PHY for DIMM version ; UMC 55nm SP/RVT LowK Logic Process Analog_IP 55nm Silver
FXDDR3COMP300HF0A Compensation Block of DDR3 Combo PHY for DIMM version ; UMC 55nm SP/RVT LowK Logic Process Analog_IP 55nm Silver
FXDDR3COMP300HF0L Compensation Block of DDR3 Combo PHY for DIMM version ; UMC 55nm LP/RVT LowK Logic Process Analog_IP 55nm Silver Minus
FXDDR3COMP400HF0A Compensation Block of DDR3/DDR3L/DDR2/LPDDR2/LPDDR Combo PHY; UMC 55nm SP/RVT LowK Logic Process Analog_IP 55nm Silver
FXDDR3COMP400HF0A Compensation Block of DDR3/DDR3L/DDR2/LPDDR2/LPDDR Combo PHY; UMC 55nm SP/RVT LowK Logic Process Analog_IP 55nm Silver
FXDDR3COMP400HF0A Compensation Block of DDR3/DDR3L/DDR2/LPDDR2/LPDDR Combo PHY; UMC 55nm SP/RVT LowK Logic Process Analog_IP 55nm Silver
FXDDR3COMP400HF0L Compensation Block of DDR3/DDR3L/DDR2/LPDDR2/LPDDR Combo PHY; UMC 55nm LP/RVT LowK Logic Process Analog_IP 55nm Bronze
 
Interface Solution > DDR
> DDR PHY - Data Block > DDR1 - Data Block 
Cell Name Descriptions Type Process Gradation Literature
FXDDR1D173HF0A DDR1/MDDR PHY Data block ; UMC 55nm SP/RVT with 2.5V device LowK Logic Process Analog_IP 55nm Bronze
 
 
Interface Solution > DDR
> DDR PHY - Data Block > DDR2 - Data Block 
Cell Name Descriptions Type Process Gradation Literature
FXDDR2D173HF0A DDR2/MDDR COMBO PHY Data block for Chip usage ; UMC 55nm SP/RVT with 2.5V device LowK Logic Process Analog_IP 55nm Silver
FXDDR2D174HF0A DDR2/MDDR Combo PHY data block ; UMC 55nm SP process with 2.5V device Analog_IP 55nm Silver
 
Interface Solution > DDR
> DDR PHY - Data Block > DDR3/3L - Data Block 
Cell Name Descriptions Type Process Gradation Literature
FXDDR3D300HF0A Data Block of DDR3 Combo PHY for DIMM version ; UMC 55nm SP/RVT LowK Logic Process Analog_IP 55nm Silver
FXDDR3D300HF0A Data Block of DDR3 Combo PHY for DIMM version ; UMC 55nm SP/RVT LowK Logic Process Analog_IP 55nm Silver
FXDDR3D300HF0L Data Block of DDR3 Combo PHY for DIMM version ; UMC 55nm LP/RVT LowK Logic Process Analog_IP 55nm Silver Minus
FXDDR3D402HF0A Data Block of DDR3/DDR3L/DDR2/LPDDR2/LPDDR Combo PHY for Chip Application; UMC 55nm SP/RVT LowK Logic Process Analog_IP 55nm Silver
FXDDR3D402HF0A Data Block of DDR3/DDR3L/DDR2/LPDDR2/LPDDR Combo PHY for Chip Application; UMC 55nm SP/RVT LowK Logic Process Analog_IP 55nm Silver
FXDDR3D403HF0A Data Block of DDR3/DDR3L/DDR2/LPDDR2/LPDDR Combo PHY for Chip Application; UMC 55nm SP/RVT LowK Logic Process Analog_IP 55nm Silver
FXDDR3D412HF0L Data Block of DDR3/DDR3L/DDR2/LPDDR2/LPDDR Combo PHY for Chip Application; UMC 55nm LP/RVT LowK Logic Process Analog_IP 55nm Bronze
FXDDR3D502HF0A Data Block of DDR3/DDR3L/DDR2/LPDDR2/LPDDR Combo PHY for Chip Application (compliant to DFI); UMC 55nm SP/RVT LowK Logic Process Analog_IP 55nm Contact Sales
 
 
Interface Solution > LVDS
> FPD LVDS Receiver 
Cell Name Descriptions Type Process Gradation Literature
FXLVRX023HF0A DLL-based LVDS RX 3.3v/1.0v ; 55nm SP/RVT LowK Logic Process Analog_IP 55nm Contact Sales
 
FXLVRX024HF0A 55nm-SP, FPD-Link Receiver, 3.3V/1.0V, 4 data plus 1 clock channel, 16~85MHz, DLL type, Analog_IP 55nm Contact Sales
FXLVRX025HF0A DLL-based LVDS RX 3.3v/1.0v ; 55nm SP/RVT LowK Logic Process Analog_IP 55nm Contact Sales
 
FXLVRX030HF0A Low power LVDS Receiver IO 500Mbps; UMC 55nm SP/RVT LowK Logic Process Analog_IP 55nm Silver
FXLVRX060HF0A DLL-based LVDS RX ; 55nm SP/RVT LowK Logic Process Analog_IP 55nm Silver
FXLVRX080HF0F LVDS RX IO PAD 300 Mbps with combo GPIO , UMC 55nm eflash/RVT LowK Logic Process Analog_IP 55nm Silver
FXLVRX080HF0L LVDS RX IO PAD 500 Mbps ,UMC 55nm LP/RVT LowK Logic Process Analog_IP 55nm Silver
FXLVRX4312HF0A 4-Data Channel DLL-based LVDS RX ; 55nm SP/RVT LowK Logic Process ; 3.3V IO / 1.0V Core ; Clock Range 10Mhz~180Mhz Analog_IP 55nm Contact Sales
FXLVRXBS080HF0F The bias block only for FXLVRX080HF0F, UMC 55nm eflash/RVT LowK Logic Process Analog_IP 55nm Contact Sales
 
FXLVRXBS080HF0L The bias block only for FXLVRX080HF0L, UMC 55nm LP/RVT LowK Logic Process Analog_IP 55nm Contact Sales
 
 
Interface Solution > LVDS
> FPD LVDS Transmitter 
Cell Name Descriptions Type Process Gradation Literature
FXLVTX020HF0A 2.5V LVDS Transmitter 16~178MHz; 55nm SP/RVT LowK Logic Process Analog_IP 55nm Silver
FXLVTX030HF0A 2.5V LVDS Transmitter 700Mbps; UMC 55nm SP LowK Logic Process Analog_IP 55nm Silver
FXLVTX033HF0A 3.3V LVDS Transmitter 700Mbps;UMC 55nm SP/RVT LowK PROCESS Analog_IP 55nm Silver
FXLVTX100HF0A 100MHz Reference Clock Single-end to Differential Buffer for PCIE Gen.II; UMC 55nm SP/RVT LowK Logic Process Analog_IP 55nm Silver Minus
 
FXLVTX320HF0A 3.3V LVDS Transmitter 16~100MHz; 55nm SP/RVT LowK Logic Process Analog_IP 55nm Silver
 
Interface Solution > MIPI
> MIPI DPHY > MIPI DPHY Receiver 
Cell Name Descriptions Type Process Gradation Literature
FXMPRX010HF0A MIPI Receiver 80Mbps ~ 1.5Gbps; UMC 55nm SP/RVT LowK Logic Process Analog_IP 55nm Silver Minus
 
Interface Solution > MIPI
> MIPI DPHY > MIPI DPHY Transmitter 
Cell Name Descriptions Type Process Gradation Literature
FXMPTX010HF0A MIPI Transmitter 80Mbps~1.5Gbps; UMC 55nm SP/RVT LowK Logic Process Analog_IP 55nm Silver Minus
 
Interface Solution > PCI Express
> PCIe PHY > PCIe-GEN2 PHY 
Cell Name Descriptions Type Process Gradation Literature
FXPCIE268HF0A PCIE Gen.II ; UMC 55nm SP/RVT LowK Logic Process Analog_IP 55nm Silver
 
Interface Solution > Serial ATA
> 3G/1.5G SATA 
Cell Name Descriptions Type Process Gradation Literature
FXSATA268HF0A Serial ATA I,II PHY ;UMC 55nm SP/RVT LowK Logic Process Analog_IP 55nm Contact Sales
 
 
Interface Solution > Serial ATA
> SATA I,II,III 
Cell Name Descriptions Type Process Gradation Literature
FXSATA368HF0A Serial ATA I,II,III PHY ; UMC 55nm SP/RVT LowK Logic Process Analog_IP 55nm Silver
 
Interface Solution > USB/OTG
> USB PHY > USB 1.1 OTG PHY 
Cell Name Descriptions Type Process Gradation Literature
FZOTG111HF0F USB1.1 PHY Feature USB 1.1 On-The-Go PHY; UMC 55nm Logic e-Flash Process Analog_IP 55nm Bronze
 
FZOTG111HF0L USB1.1 PHY Feature USB 1.1 On-The-Go PHY; UMC 55nm Logic Low Power Low-K Process Analog_IP 55nm Contact Sales
 
Interface Solution > USB/OTG
> USB PHY > USB 1.1 PHY 
Cell Name Descriptions Type Process Gradation Literature
FZUSB199HF0F USB 1.1 transceiver support crystal-less mode in USB system ; UMC 55nm eFlash Process Analog_IP 55nm Silver Minus
 
Interface Solution > USB/OTG
> USB PHY > USB 2.0 OTG PHY 
Cell Name Descriptions Type Process Gradation Literature
FZOTG266HF0A OTG USB 2.0 PHY (VDT and ID are included in PHY) ; UMC 55nm SP LowK Logic Process Analog_IP 55nm Silver
FZOTG266HF0F USB2.0 OTG PHY ; UMC 55nm eFlash Process Analog_IP 55nm Silver Minus
FZOTG266HF0L USB2.0 OTG PHY (VDT and ID are included in PHY) ; UMC 55nm LP LowK Logic Process Analog_IP 55nm Silver Minus
 
Interface Solution > USB/OTG
> USB PHY > USB 3.0 OTG PHY 
Cell Name Descriptions Type Process Gradation Literature
FZOTG300HF0A USB3.0 PHY ; UMC 55nm SP/RVT LowK Logic Process Analog_IP 55nm Silver