Logic Libraries

Updated On:2018-01-21
Gradation
Faraday IPs are rated according to the IPs’ maturity and customer acceptance. They are graded by the rules described as below,


Platinum P Five (5) productions verified
Gold G Mass production proven
Silver S Silicon proven, Formal release
Silver Minus S- Manufacturing onging
Bronze B Pre-Silicon release
 
Logic Libraries > Generic Core Cell Library
> 12-Track Library 
Cell Name Descriptions Type Process Gradation Literature
FSF0F_GLS_GENERIC_CO
RE
UMC 55nm eFlash/LVT Logic Process High Speed 12-track Genernic Core cell library Library_Group 55nm Silver
 
Logic Libraries > Generic Core Cell Library
> 12-Track Library > 12T HVT Core Library 
Cell Name Descriptions Type Process Gradation Literature
FSF0A_GHS_GENERIC_CO
RE
UMC 55nm SP/HVT LowK Logic Process UHS cell library Library_Group 55nm Silver Minus
FSF0F_GHS_GENERIC_CO
RE
UMC 55nm eFlash/HVT Logic Process High Speed 12-track Genernic Core cell library Library_Group 55nm Silver
FSF0L_GHS_GENERIC_CO
RE
UMC 55nm LP/HVT LowK Logic Process 12-track generic core cell library Library_Group 55nm Silver
FSF0V_GHS_GENERIC_CO
RE
UMC 55nm HV/HVT LowK Logic Process High Speed Standard Core Library Library_Group 55nm Silver Minus
 
Logic Libraries > Generic Core Cell Library
> 12-Track Library > 12T LVT Core Library 
Cell Name Descriptions Type Process Gradation Literature
FSF0L_GLS_GENERIC_CO
RE
UMC 55nm LP/LVT LowK Logic Process 12-Tracks Generic Core Cell Library Library_Group 55nm Silver
 
Logic Libraries > Generic Core Cell Library
> 12-Track Library > 12T RVT Core Library 
Cell Name Descriptions Type Process Gradation Literature
FSF0A_GRS_GENERIC_CO
RE
UMC 55nm SP-RVT LowK Process high-speed core cell library Library_Group 55nm Silver Minus
FSF0F_GRS_GENERIC_CO
RE
UMC 55nm eFlash/RVT Logic Process High Speed 12-track Genernic Core cell library Library_Group 55nm Silver
FSF0L_GRS_GENERIC_CO
RE
UMC 55nm LP/RVT LowK Logic Process 12-Tracks Generic Core Cell Library Library_Group 55nm Silver