Analog

Updated On:2018-06-21
Gradation
Faraday IPs are rated according to the IPs’ maturity and customer acceptance. They are graded by the rules described as below,


Platinum P Five (5) productions verified
Gold G Mass production proven
Silver S Silicon proven, Formal release
Silver Minus S- Manufacturing onging
Bronze B Pre-Silicon release
 
Analog > A/D Converter
> SAR ADC > 12Bit SAR ADC 
Cell Name Descriptions Type Process Gradation Literature
FXADC125HF0U UMC 55uLP ADC Power: 100k sps < 24uA (TT) 1Msps < 240uA (TT) 5Msps < 1000uA (TT) Inactive < TBD (TT) (Inactive to Active: 4 cycle) Max. sampling: 5M sps VDDA: 1.8V (TT) 1.62V~ 1.98V (ADC and Temp. sensor) VCCK: 1.2V(TT) 0.81V~1.32V (ADC and Temp. sensor) Vref (cap): 1.2V (default) programmable (1.2V, 1.3V, 1.4V and 1.5V), derived from VDDA (Built-in LDO for XVRT; XVRB=GND) fADC clock: 26MHz~ 80MHz Resolution: 12-bit Divider Disable/enable: bridge divider by 4, 3, 2, 1 channel number: 5 ADC Channel assignment: *ADC1: 1 ch with PAD (outside); ADC2: 2 ch with PAD *ADC1: 1 ch for temperature sensor; ADC2: No need to have temperature sensor Temperature Sensor Power: Operation current < 4.7uA (TT) Inactive < TBD(TT) Temperature Sensor Accuracy: +/- 3℃ after calibrated by Faraday in CP or FT Analog_IP 55nm Contact Sales
 
FXADC1502HF0G 12Bit 1Msps SAR-ADC based on UMC 55nm uLP eflash process (GPIO Function integrated) Analog_IP 55nm Silver Minus
FXADC1502HF0L_FTCM8A 12bit 1MSPS SAR ADC with 8-1 Mux (All C-type) ; UMC 55nm LP/RVT Logic Process Analog_IP 55nm Silver
FXADC1502HF0U_FTCM8A 12Bit 1Msps SAR-ADC based on UMC 55nm uLP process Analog_IP 55nm Contact Sales
 
FXADC1642HF0F Low power 12bit 4Msps SAR ADC with UMC 55nm EFLASH Process Analog_IP 55nm Silver Minus
FXADC1722HF0F A 12bit 2Msps low power and large voltage range SAR-ADC based on UMC 55nm eflash process Analog_IP 55nm Bronze
FXADC1723HF0F A 12bit 2Msps low power and large voltage range SAR-ADC based on UMC 55nm eflash process Analog_IP 55nm Contact Sales