Analog

Updated On:2018-04-25
Gradation
Faraday IPs are rated according to the IPs’ maturity and customer acceptance. They are graded by the rules described as below,


Platinum P Five (5) productions verified
Gold G Mass production proven
Silver S Silicon proven, Formal release
Silver Minus S- Manufacturing onging
Bronze B Pre-Silicon release
 
Analog > Clock
> DDR DLL > 20M ~ 500M, DDR DLL 
Cell Name Descriptions Type Process Gradation Literature
FXDLL310HF0A Input 200-400MHz, output 200-400MHz, DDR2 DLL; UMC 55nm SP Low-K Logic Process Analog_IP 55nm Silver
FXDLL340HF0A Input 80-320MHz, output 6.25%~50% delay,80-320MHz, DDR2 DLL; UMC 55nm SP/RVT LowK Logic Process Analog_IP 55nm Silver