Interface Solution

Updated On:2018-04-24
Gradation
Faraday IPs are rated according to the IPs’ maturity and customer acceptance. They are graded by the rules described as below,


Platinum P Five (5) productions verified
Gold G Mass production proven
Silver S Silicon proven, Formal release
Silver Minus S- Manufacturing onging
Bronze B Pre-Silicon release
 
Interface Solution > LVDS
> FPD LVDS Receiver 
Cell Name Descriptions Type Process Gradation Literature
FXLVRX023HF0A DLL-based LVDS RX 3.3v/1.0v ; 55nm SP/RVT LowK Logic Process Analog_IP 55nm Contact Sales
 
FXLVRX024HF0A 55nm-SP, FPD-Link Receiver, 3.3V/1.0V, 4 data plus 1 clock channel, 16~85MHz, DLL type, Analog_IP 55nm Contact Sales
FXLVRX025HF0A DLL-based LVDS RX 3.3v/1.0v ; 55nm SP/RVT LowK Logic Process Analog_IP 55nm Contact Sales
 
FXLVRX030HF0A Low power LVDS Receiver IO 500Mbps; UMC 55nm SP/RVT LowK Logic Process Analog_IP 55nm Silver
FXLVRX060HF0A DLL-based LVDS RX ; 55nm SP/RVT LowK Logic Process Analog_IP 55nm Silver
FXLVRX080HF0F LVDS RX IO PAD 300 Mbps with combo GPIO , UMC 55nm eflash/RVT LowK Logic Process Analog_IP 55nm Silver
FXLVRX080HF0L LVDS RX IO PAD 500 Mbps ,UMC 55nm LP/RVT LowK Logic Process Analog_IP 55nm Silver
FXLVRX4312HF0A 4-Data Channel DLL-based LVDS RX ; 55nm SP/RVT LowK Logic Process ; 3.3V IO / 1.0V Core ; Clock Range 10Mhz~180Mhz Analog_IP 55nm Contact Sales
FXLVRXBS080HF0F The bias block only for FXLVRX080HF0F, UMC 55nm eflash/RVT LowK Logic Process Analog_IP 55nm Contact Sales
 
FXLVRXBS080HF0L The bias block only for FXLVRX080HF0L, UMC 55nm LP/RVT LowK Logic Process Analog_IP 55nm Contact Sales