Interface Solution

Updated On:2018-01-20
Gradation
Faraday IPs are rated according to the IPs’ maturity and customer acceptance. They are graded by the rules described as below,


Platinum P Five (5) productions verified
Gold G Mass production proven
Silver S Silicon proven, Formal release
Silver Minus S- Manufacturing onging
Bronze B Pre-Silicon release
 
Interface Solution > LVDS
> FPD LVDS Transmitter 
Cell Name Descriptions Type Process Gradation Literature
FXLVTX020HF0A 2.5V LVDS Transmitter 16~178MHz; 55nm SP/RVT LowK Logic Process Analog_IP 55nm Silver
FXLVTX030HF0A 2.5V LVDS Transmitter 700Mbps; UMC 55nm SP LowK Logic Process Analog_IP 55nm Silver
FXLVTX033HF0A 3.3V LVDS Transmitter 700Mbps;UMC 55nm SP/RVT LowK PROCESS Analog_IP 55nm Silver
FXLVTX100HF0A 100MHz Reference Clock Single-end to Differential Buffer for PCIE Gen.II; UMC 55nm SP/RVT LowK Logic Process Analog_IP 55nm Silver Minus
 
FXLVTX320HF0A 3.3V LVDS Transmitter 16~100MHz; 55nm SP/RVT LowK Logic Process Analog_IP 55nm Silver