Interface Solution

Updated On:2018-01-22
Faraday IPs are rated according to the IPs’ maturity and customer acceptance. They are graded by the rules described as below,

Platinum P Five (5) productions verified
Gold G Mass production proven
Silver S Silicon proven, Formal release
Silver Minus S- Manufacturing onging
Bronze B Pre-Silicon release
Interface Solution > DDR
> DDR IO > DDR2 - SSTL18 IO Library 
Cell Name Descriptions Type Process Gradation Literature
55LP DDR1/DDR2 IO. 1. U55 LP Process 2. DDR2/DDR1 IO -2.5V SSTL2/1.8 SSTl18 ( CMOS/SSTL) –4 Driving strength @ Target: DDR 533 Mbps( IO 266 MHz) -VCCK Core power-off, All IO pull low Library_Group 55nm Contact Sales