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職務名稱 |
徵才條件 |
工作地點 |
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廠務管理師 |
1.廠務系統維護與管理，並執行設備定期保養及故障修繕
2.系統優化及工程改善評估
3.節能項目可行性評估與改善
4.設備異常緊急應變處理
5.消防管理
6.ESG報告書環境永續相關章節撰寫
7.其他交辦工作
其他條件:
1.具(丙級/乙級)室內配線技術士/甲種電匠證照
2.具能源管理人員訓練合格證書
3.具防火管理人證照
4.具ISO 50001能源管理系統導入驗證及實務運作經驗者尤佳
5.細心、邏輯性強
6.積極正向、情緒管理佳、具備同理心 |
新竹 |
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Windows 系統工程師 |
1.負責VMWare VDI相關系統的規劃與管理
2.負責Exchange Online、Exchange SE相關應用服務與策略的規劃與管理
其他條件:
1.資訊工程相關學科，大學學歷畢業
2.熟悉虛擬化環境(VMWare VDI)的規劃、建置與管理
3.熟悉 Exchange Online、Exchange SE管理
4.良好的溝通能力並能與其他部門、團隊合作
【擅長工具】VMWare vSphere
Exchange Online、Exchange SE
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新竹 |
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PLL DLL Design Engineer |
General OSC/PLL/DLL/SSCG/CDR design & production experience
1) LC-tank VCO design & production experience
2) CDR design & production experience
其他條件:
Capable to communicate in English is a strong plus.(TOEIC 700 above is preferred.) |
新竹 |
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資深高速混合信號Mix-Mode 數位IC設計工程師 |
high resolution Delta-sigma codec (for audio , FNPLL , sensor )混合訊號介面之數位IC設計
其他條件:
1. Knowledge and design experience of IC digital flows & FPGA validations
2. Knowledge and design experience ( at least one of ADPLL, ADCDR, ADSSCG, DSPLL and Delta-sigma codec. )
3. Hands-on experience on post-silicon debug
4. DSP knowledge and background (FIR, IIR, ECC,...etc)
5. Capable to communicate in English is a strong plus.(TOEIC 700 above is preferred.) |
新竹 |
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高速混合信號Mix-Mode 數位IC設計工程師 |
USB/SATA/PCI Express/Ethernet/VBO/MIPI相關高速混合訊號介面之數位IC設計
其他條件:
1. One of the key Serdes protocol (PCIe, SATA, USB.Ethernet,VBO,MIPI etc)
2. Knowledge and design experience of PCS
3. Knowledge and design experience of digital flows & FPGA validations
4. Hands-on experience on post-silicon debug
5. DSP knowledge . scrambling is minimum; best to have knowledge on multiple DSP background (FEC, FFE, FIR, IIR, ECC,...etc)
6. Capable to communicate in English is a strong plus.(TOEIC 700 above is preferred.)
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新竹 |
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技術行銷工程師 |
1. Product planning, including market survey, positioning and customer engament, for IP and application.
2. Strategic analysis for process & IP development, potential customers and applications.
3. Lead cross functional teams to architect solutions for new market and applications.
其他條件:
1. 3+ years of working experience.
2. Experience in coordinating cross functional Engineering efforts
3. Excellent verbal and written English communication ability .(TOEIC 800 above is preferred .)
4. MS in EE or relative field |
新竹 |
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Physical Verification CAD engineer |
1. Foundry & In-house DRC/LVS/LPE/PERC rule deck maintain & creation
2. Physical verification CAD flow establishment & maintenance
3. Issue solving for ASIC project & IP development DRC/LVS problem
其他條件:
1. 熟 C/C++ or Perl/TCL/C-shell scrpit.
2. 熟悉 Laker or Virtuoso
3. 熟悉 Calibre or ICV or PVS |
新竹 |
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SOC Physical Design Engineer-台北 |
1. Responsible for ASIC physical implementation by using automatic place and route tools. The P&R processes including floorplanning, power plan synthesis and analysis, physical timing optimization, clock tree synthesis, routing, and post-routing optimizations.
2. Responsible for physical verification including DRC, LVS and ESD checking.
其他條件:
俱有advanced node process經驗優先
1. BS or MS degree in EE or CS related
2. Experienced in Cadence Innovus flow or Synopsys ICC2 flow
3. Experienced in hierarchical implementation, timing closure, IR drop analysis, crosstalk analysis is a plus
4. Experienced in physical verification and layout editing is a plus |
台北 |
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數位IC驗證工程師 |
IP驗證
-驗證計畫制定 (Verification Planning)
-驗證環境開發 (Environment Development)
-測試執行與除錯 (Execution & Debugging)
-覆蓋率收斂 (Coverage Closure)
其他條件:
1. 熟悉 Verilog, SystemVerilog coding
2. 熟悉 UVM (Universal Verification Methodology)
3. 開發 VIP 或使用 VIP 有經驗
4. 有USB/SATA/PCIE/DDR/MIPI經驗尤佳 |
新竹 |
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Power Management Designer (台南/新竹) |
Power management design:
1) BG design
2) LDO design
3) DC/DC switching power regulator design
其他條件:
1) Familiar with BG and LDO design
2) Familiar with DC/DC switching power regulator design
3) Capable to communicate in English is a strong plus.(TOEIC 700 above is preferred.)
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台南 |
