Architecture Exploration and Performance Verification for Complex SoCs

Architecture exploration and performance verification are critical in the early stages of developing complex SoCs. To help customers create competitive SoC products, Faraday collaborates with them from bus architecture design to application flow optimization, providing the essential components and methodologies to address performance challenges in both hardware and software.

Under Faraday's SoC design service, both the performance exploration platforms and virtual platforms are available to meet comprehensive architecture design requirements. By utilizing various efficient platforms and adopting network-on-chip (NoC) technology, Faraday enhances capabilities and flexibility in tackling complex, large-scale SoC designs.

Performance Exploration Platform

An exploration platform can be established in the project's early phase to assess and validate chip architecture performance. Essential components, such as traffic generators and performance monitors, are created accordingly. This architecture exploration methodology has been successfully applied in numerous projects.

Virtual Platform

Faraday leverages Transaction-Level Modeling (TLM) technology for efficient IP modeling, facilitating the development of virtual platforms. This approach has become standard practice in the industry to accelerate software availability, and workflows for performance simulation can be derived from this facility.

Network-on-Chip 

Network-on-Chip (NoC) is an emerging paradigm for communication within SoCs, replacing traditional bus architectures. It offers the flexibility to connect widely distributed IPs in large-scale SoCs while alleviating routing congestion issues. This technology has been successfully implemented in several large-scale SoC projects at Faraday, supported by mature workflows and methodologies to address front-end and back-end iterations for timing closure.