Memory Compiler Architecture       Type Description 1-Port SRAM synchronous high density one port RAM Dual Port SRAM synchronous high density two ports RAM 1 Port Register File sychronous one port register file 2 Ports Register File sychronous two ports register file Via ROM sync via1 programmed ROM   Delivery Package There are two types of packages we could deliver to our customers. One is the Design Kit and the other is the Tape-out Kit. You are welcomed to download our database for evaluation.       Design Kit Package Name Deliverables EDA Views Design Package Synthesis model Synopsys Simulation model Cadence Verilog-XL Synopsys VSS (VHDL) ATPG model Mentor Fastscan Document Databook & Release Notes P&R model in physical Cadence LEF Tape-out kit Package Name Deliverables EDA Views Tape out package Netlist LVS netlist,Post-sim circuit netlist Physical Layout GDSII Standard Format