Foundry Technology

Faraday is the long term partner of UMC for alpha site of process developing with more than two decades. To accompany and combine UMC's leading-edge process models and technologies in early stage has enabled us to develop the fundamental IPs before the process has been released. Meanwhile, UMC can enhance the process receipt and simulation models to get better results of performance and leakage for ASIC implementation according to Faraday's IP silicon results.

In order to meet the growing demand of advanced MCU-related and IoT applications, Faraday has successfully extended 55nm node collaboration with UMC, aiming to provide high performance, low power solutions for customers to lower the integration risk and shorten the time-to-market.

UMC's 55nm ULP (ultra-low power) technology can support both lower operating voltage and sub-pA device leakage, making the process ideal for button-cell battery applications. Chip designers can take advantage of UMC’s low power technology as a foundation.

 

Availability of 55ULP Process

Items Sub-Items 55LP 55ULP
Process Baseline Optimized 55LP
Operation Voltage 1.2V 0.9V
Logic Device LVT

V

V
RVT V V
HVT V V
uHVT - V
6T SRAM Bit-cell size 0.425um² 0.525um²
(Low Standby SRAM)
Vccmin 1.08V 0.81V
Isb (pA/cell) 12.10 (1.2V) 4.68 (1.2V) 1.28 (0.9V)

 

Technology Comparison