Design Flow

To help customers implement their chip designs in physical silicon, Faraday offers efficient, reliable and full-spectrum design methodology and tools. Faraday's design methodology adopts leading edge commercial EDA tools as well as proprietary utilities to form a streamlined process for today's ASIC design.

Faraday's major design methodology features include the following: feasibility analysis, timing closure solutions, power-integrity solutions, signal-integrity solutions, reliability solutions, complexity solutions, testability solutions, design for manufacturability, and low-power solutions, etc.


EDA Tools
Design flow and third-party EDA tool support

Design Flow Task 3rd Party EDA Tool
Design implementation Logic synthesis Synopsys Design Compiler
Cadence RTL Compiler
Incentia DesignCraft
Design for test Synopsys DFT Compiler
Incentia TestCraft
Mentor Graphics Tessent MBIST
Mentor Graphics Tessent TestKompress
Synopsys BSD Compiler
Floorplanning Cadence Encounter EDI
Physical implementation Cadence Encounter EDI
Synopsys IC Compiler
ATopTech Aprisa
RC extraction Cadence QRC
Mentor Graphics xRC
Engineering change order (ECO) Dorado Tweaker
Cadence Conformal ECO
Design verification Static timing analysis Synopsys PrimeTime
Cadence ETS
Timing constraint validation Cadence Conformal CCD
Formal verification Cadence Conformal LEC
Low power verification Cadence Conformal CLP
Simulation Cadence NC-Sim
Mentor Graphics ModelSim
Synopsys VCS
Test structure verification Mentor Graphics FastScan
Physical verification Mentor Graphics Calibre
Design Analysis RTL code purification Synopsys LEDA
Power noise analysis Cadence EPS
Apache Redhawk
Waveform analysis Synopsys Verdi
Crosstalk analysis Cadence ETS
Synopsys PrimeTime-SI
Package PI/SI Ansys HFSS
Cadence Sigrity PowerSI/ExtractIM

Design Stage and Faraday's Proprietary Design Kits

Design Entry/Review
- fsize estimates chip size based on preliminary information.
- powersheet provides power estimation in specification level.
- fcpfgen provides low power design spec. (CPF) generation and review GUI interface.
Design Planning
- face checks the RTL quality, including code purification and code coverage.
- fpgc optimizes the number of power/ground pins and its location to minimize SSN (Simultaneously Switching Noise).
- ftcv performs sdc timing constraint validation.
- testplan provides an integrated environment for DFT synthesis integration.
- mkbnd provides package bonding simulation to check the feasibility of pad location.
Design Implementation
- fiolt inserts DFT and generates test pattern for IO level DC testing.
- fscan inserts scan chain and test compression DFT.
- fbsd inserts IEEE 1149.1 boundary scan DFT and generates its test patterns.
- fmbist inserts memory BIST and generates its test patterns.
- feco provides user-friendly tcl interface for manual ECO.
- flec-eco provides an easy interface for function ECO by giving golden design and to-be-ECO netlist
- ftwk provides an integrated environment for timing closure ECO
Design Verification
- powercat provides a gate-level cycle-based power calculation.
- fcdc calculates pre-layout SDF cell delay for simulation and STA.
- flec simplifies and accelerates the process of formal verification.
- flec-clp checks the consistency between low power design spec. and the implemented netlist.
- fsim provides an easy environment for simulation with third-party tools.
- fesd detects all possible ESD crisis path if there is more than one power domain.
- fisb indentifies the appropriate cycle in the test pattern for standby current measurement.
- fsta provides an integrated environment for timing constraints validation and STA with third-party tools.
- fppg analyzes power noise including IR-drop and electro-migration.
- fipcon checks the consistency of IP test integration with the original design spec.

PowerSmart® - Low-Power Design Methodology
Power considerations have become a dominant factor in system design, especially in portable, battery-powered systems. Currently, system designers must work closely with both circuit and foundry engineers to manage power, requiring cross-functional expertise and straining resources for the integrated approach. At Faraday, we recognize the difficulties of system design and have developed the PowerSmart® design service to help our customers expedite their ideas into silicon