PowerSlash Core Cell Library

Updated On:2018-07-20
Gradation
Faraday IPs are rated according to the IPs’ maturity and customer acceptance. They are graded by the rules described as below,


Platinum P Five (5) productions verified
Gold G Mass production proven
Silver S Silicon proven, Formal release
Silver Minus S- Manufacturing onging
Bronze B Pre-Silicon release
 
Logic Libraries > PowerSlash Core Cell Library
> 10-Track > 10T HVT PSK Library 
Cell Name Descriptions Type Process Gradation Literature
FSD0C_G_POWERSLASH_C
ORE
UMC 90nm SP-HVT LowK Logic Process High Speed PowerSlash Kit Library_Group 90nm Contact Sales
 
 
Logic Libraries > PowerSlash Core Cell Library
> 10-Track > 10T RVT PSK Library 
Cell Name Descriptions Type Process Gradation Literature
FSD0A_G_POWERSLASH_C
ORE
UMC 90nm SP-RVT LowK Logic Process High Speed PowerSlash Kit Library_Group 90nm Contact Sales
 
 
Logic Libraries > PowerSlash Core Cell Library
> 12-Track 
Cell Name Descriptions Type Process Gradation Literature
FSF0F_GLS_POWERSLASH
_CORE
UMC 55nm eFlash/LVT Logic Process High Speed 12-track PowerSlash Kit cell library Library_Group 55nm Silver
FSH0L_GLS_POWERSLASH
_CORE
UMC 40nm LP/LVT Logic Process 12-track powerslash core cells Library_Group 40nm Bronze
FSH0L_GRS_POWERSLASH
_CORE
UMC 40nm LP/RVT LowK Logic Process 12-track Powerslash Cell Library Library_Group 40nm Bronze
FSJ0C_HHS_POWERSLASH
_CORE
UMC 28nm HPC/HVT Logic and Mixed-Mode Process 12-track POWERSLASH cell library enhanced for routing (C35) Library_Group 28nm Contact Sales
 
FSJ0C_HLS_POWERSLASH
_CORE
UMC 28nm HPC/LVT Logic and Mixed-Mode Process 12-track POWERSLASH cell library enhanced for routing (C35) Library_Group 28nm Bronze
FSJ0C_HRS_POWERSLASH
_CORE
UMC 28nm HPC/RVT Logic and Mixed-Mode Process 12-track POWERSLASH cell library enhanced for routing (C35) Library_Group 28nm Contact Sales
 
 
Logic Libraries > PowerSlash Core Cell Library
> 12-Track > 12T HVT PSK Library 
Cell Name Descriptions Type Process Gradation Literature
FSF0F_GHS_POWERSLASH
_CORE
UMC 55nm eFlash/HVT Logic Process High Speed 12-track PowerSlash Kit cell library Library_Group 55nm Silver
FSF0L_GHS_POWERSLASH
_CORE
UMC 55nm LP/HVT LowK Logic Process 12-track generic core cell library Library_Group 55nm Silver
FSH0L_HHS_POWERSLASH
_CORE
UMC 40nm LP/HVT Logic Process 12-Track High Speed Cell PowerSlash Library (C40) Library_Group 40nm Silver
 
FSJ0C_GHS_POWERSLASH
_CORE
UMC 28nm HPC/HVT Logic and Mixed-Mode Process 12-track PowerSlash cell library (C35) Library_Group 28nm Bronze
FSJ0L_GHS_POWERSLASH
_CORE
UMC 28nm Logic and Mixed-Mode HLP/HVT Process 12-track PowerSlash Cell library (C35) Library_Group 28nm Silver
FSJ0L_HHS_POWERSLASH
_CORE
UMC 28nm HLP Process C35 HVT Library (FSJ0L_HHS) PowerSlash Library_Group 28nm Bronze
 
Logic Libraries > PowerSlash Core Cell Library
> 12-Track > 12T LVT PSK Library 
Cell Name Descriptions Type Process Gradation Literature
FSF0L_GLS_POWERSLASH
_CORE
UMC 55nm LP/LVT LowK Logic Process 12-Tracks Powerslash Core Cell Library Library_Group 55nm Silver
FSH0L_HLS_POWERSLASH
_CORE
UMC 40nm LP/LVT Logic Process 12-Track High Speed Powerslash Core Cell Library Library_Group 40nm Silver
FSJ0C_GLS_POWERSLASH
_CORE
UMC 28nm HPC/LVT Logic and Mixed-Mode Process 12-track PowerSlash cell library (C35) Library_Group 28nm Bronze
FSJ0L_GLS_POWERSLASH
_CORE
UMC 28nm Logic and Mixed-Mode HLP/LVT Process 12-track PowerSlash cell library (C35) Library_Group 28nm Silver
FSJ0L_HLS_POWERSLASH
_CORE
UMC 28nm HLP Process C35 LVT Library (FSJ0L_HLS) PowerSlash Library_Group 28nm Bronze
 
Logic Libraries > PowerSlash Core Cell Library
> 12-Track > 12T RVT PSK Library 
Cell Name Descriptions Type Process Gradation Literature
FSF0A_GRS_POWERSLASH
_CORE
UMC 55nm SP/RVT LowK Logic Process UHS library PSK cells Library_Group 55nm Bronze
 
FSF0F_GRS_POWERSLASH
_CORE
UMC 55nm eFlash/RVT Logic Process High Speed 12-track PowerSlash Kit cell library Library_Group 55nm Silver
FSF0L_GRS_POWERSLASH
_CORE
UMC 55nm LP/RVT LowK Logic Process 12-Tracks Powerslash Core Cell Library Library_Group 55nm Silver
FSH0L_HRS_POWERSLASH
_CORE
UMC 40nm LP/RVT Logic Process 12-Track High Speed PowerSlash Cell Library (C40) Library_Group 40nm Silver
FSJ0C_GRS_POWERSLASH
_CORE
UMC 28nm HPC/RVT Logic and Mixed-Mode Process 12-track PowerSlash cell library (C35) Library_Group 28nm Bronze
 
FSJ0L_GRS_POWERSLASH
_CORE
UMC 28nm Logic and Mixed-Mode HLP/RVT Process 12-track Standard POWERSLASH core cell library (C35) Library_Group 28nm Silver
FSJ0L_HRS_POWERSLASH
_CORE
UMC 28nm HLP Process C35 RVT Library (FSJ0L_HRS) PowerSlash Library_Group 28nm Bronze
 
Logic Libraries > PowerSlash Core Cell Library
> 6-Track > 6T HVT PSK Library 
Cell Name Descriptions Type Process Gradation Literature
FSF0U_JHA_POWERSLASH
_CORE
UMC 55nm ULP/HVT Low-K Logic Process Process 6-track Powerslash Cell Library (C90) Library_Group 55nm Silver
FSF0U_JHB_POWERSLASH
_CORE
UMC 55nm ULP/HVT Low-K Logic Process Process 6-track Powerslash Cell Library (C60). W/O deep Nwell Library_Group 55nm Silver
FSF0U_JHS_POWERSLASH
_CORE
UMC 55nm ULP/HVT Low-K Logic Process Process 6-track Powerslash Cell Library (C60) w/ Forward Bias. W/ deep Nwell Library_Group 55nm Silver
FSF0U_JHU_POWERSLASH
_CORE
UMC 55nm ULP/HVT Low-K Logic Process Process 6-track Powerslash Cell Library (C90) w/ Forward Bias. W/ deep Nwell. Library_Group 55nm Silver
 
Logic Libraries > PowerSlash Core Cell Library
> 6-Track > 6T LVT PSK Library 
Cell Name Descriptions Type Process Gradation Literature
FSF0U_JLS_POWERSLASH
_CORE
UMC 55nm ULP/LVT Low-K Logic Process Process 6-track Powerslash Cell Library (C60).W/O deep Nwell. Library_Group 55nm Silver
 
Logic Libraries > PowerSlash Core Cell Library
> 6-Track > 6T RVT PSK Library 
Cell Name Descriptions Type Process Gradation Literature
FSF0U_JRS_POWERSLASH
_CORE
UMC 55nm ULP/RVT Low-K Logic Process Process 6-track Powerslash Cell Library (C60). W/O deep Nwell. Library_Group 55nm Silver
 
Logic Libraries > PowerSlash Core Cell Library
> 6-Track > 6T uHVT PSK Library 
Cell Name Descriptions Type Process Gradation Literature
FSF0U_JUU_POWERSLASH
_CORE
UMC 55nm ULP/uHVT Low-K Logic Process Process 6-track Powerslash Cell Library (C90) w/ Forward Bias. W/ deep Nwell. Library_Group 55nm Silver
 
Logic Libraries > PowerSlash Core Cell Library
> 7-Track > 7T HVT PSK Library 
Cell Name Descriptions Type Process Gradation Literature
FSC0H_J_POWERSLASH_C
ORE
UMC 0.13um HS/FSG Process FSC0H_J PowerSlashKit core library Library_Group 0.13um Bronze
FSD0C_E_POWERSLASH_C
ORE
UMC 90nm SP-HVT LowK process power slash core cell libary Library_Group 90nm Bronze
FSD0J_E_POWERSLASH_C
ORE
UMC 90nm LL/HVT LowK Logic Process Cell Library PowerSlash Core Cell Library (High Density Version) Library_Group 90nm Bronze
FSF0A_EHS_POWERSLASH
_CORE
UMC 55nm SP/HVT Logic Process 7-track PSK cell library Library_Group 55nm Bronze
FSF0F_EHS_POWERSLASH
_CORE
UMC 55nm eFlash/HVT Logic Process 7-track PowerSlash Kit cell library Library_Group 55nm Silver
FSF0L_EHS_POWERSLASH
_CORE
UMC 55nm LP/HVT LowK Logic Process 7-Track PSK cell library Library_Group 55nm Silver
FSH0L_EHS_POWERSLASH
_CORE
UMC 40nm LP/HVT LowK Logic Process 7-track Power Slash Cell Library Library_Group 40nm Silver
FSH0V_DHS_POWERSLASH
_CORE
UMC 40nm HV/HVT Logic Process 7-Track Standard Cell Library (PowerSlash Core) Library_Group 40nm Contact Sales
FSJ0C_DHS_POWERSLASH
_CORE
UMC 28nm HPC/HVT Logic and Mixed-Mode Process 7-track PowerSlash Kit cell library C35 Library_Group 28nm Silver
FSJ0C_EHS_POWERSLASH
_CORE
UMC 28nm HPC/HVT Logic and Mixed-Mode Process 7-track POWERSLASH cell library enhanced for routing (C35) Library_Group 28nm Silver
FSJ0L_EHS_POWERSLASH
_CORE
UMC 28nm HLP/HVT Logic and Mixed-Mode Process 7-track PowerSlash Cell Library Library_Group 28nm Silver
FSJ0L_EHU_POWERSLASH
_CORE
UMC 28nm HLP/HVT Logic and Mixed-Mode Process 7-track Generic Core Cell Library with LPLUS (C-38) Library_Group 28nm Contact Sales
 
FSJ0P_EHS_POWERSLASH
_CORE
UMC 28nm HPC+/HVT Logic and Mixed-Mode Process 7-track POWERSLASH cell library enhanced for routing (C35) Library_Group 28nm Bronze
FSN0U_EHS_POWERSLASH
_CORE
UMC 22nm ULP/HVT Logic and Mixed-Mode Process 7-track POWERSLASH cell library enhanced for routing (C35) Library_Group 22nm Contact Sales
 
FSR0H_J_POWERSLASH_C
ORE
UMC 0.11um 1P8M HS/FSG Logic Process high density PSK (Power Slash) core cell library (7-grid) Library_Group 0.11um Bronze
 
Logic Libraries > PowerSlash Core Cell Library
> 7-Track > 7T LVT PSK Library 
Cell Name Descriptions Type Process Gradation Literature
FSC0L_J_POWERSLASH_C
ORE
UMC 0.13um LL FSG Logic Process high density power-slash core cell library Library_Group 0.13um Bronze
FSF0F_ELS_POWERSLASH
_CORE
UMC 55nm eFlash/LVT Logic Process 7-track PowerSlash Kit cell library Library_Group 55nm Silver
FSF0L_ELS_POWERSLASH
_CORE
UMC 55nm LP/LVT LowK Logic Process 7-Tracks Powerslash Core Cell Library Library_Group 55nm Silver
FSH0L_ELS_POWERSLASH
_CORE
UMC 40nm LP/LVT LowK Logic Process 7-track Power Slash Cell Library Library_Group 40nm Silver
FSH0V_DLS_POWERSLASH
_CORE
UMC 40nm HV/LVT Logic Process 7-Track Standard Cell Library (PowerSlash Core) Library_Group 40nm Contact Sales
FSJ0C_DLS_POWERSLASH
_CORE
UMC 28nm HPC/LVT Logic and Mixed-Mode Process 7-Track POWERSLASH cell library (C35) Library_Group 28nm Silver
FSJ0C_ELS_POWERSLASH
_CORE
UMC 28nm HPC/LVT Logic and Mixed-Mode Process 7-track POWERSLASH cell library enhanced for routing (C35) Library_Group 28nm Silver
FSJ0L_ELD_POWERSLASH
_CORE
UMC 28nm HLP/LVT Logic and Mixed-Mode Process 7-track Powerslash Cell Library with LMINUS (C-30) Library_Group 28nm Contact Sales
 
FSJ0L_ELS_POWERSLASH
_CORE
UMC 28nm HLP/LVT Logic and Mixed-Mode Process 7-track PowerSlash Cell Library Library_Group 28nm Silver
FSJ0L_ELU_POWERSLASH
_CORE
UMC 28nm HLP/LVT Logic and Mixed-Mode Process 7-track Powerslash Generic Core Cell Library wtih LPLUS (C-38) Library_Group 28nm Contact Sales
 
FSJ0P_ELS_POWERSLASH
_CORE
UMC 28nm HPC+/LVT Logic and Mixed-Mode Process 7-track POWERSLASH cell library enhanced for routing (C35) Library_Group 28nm Bronze
FSN0U_ELS_POWERSLASH
_CORE
UMC 22nm ULP/LVT Logic and Mixed-Mode Process 7-track POWERSLASH cell library enhanced for routing (C35) Library_Group 22nm Contact Sales
 
FSR0L_J_POWERSLASH_C
ORE
UMC 0.11um LL/FSG Logic Process high density power-slash core cell library Library_Group 0.11um Bronze
 
Logic Libraries > PowerSlash Core Cell Library
> 7-Track > 7T RVT PSK Library 
Cell Name Descriptions Type Process Gradation Literature
FSC0G_J_POWERSLASH_C
ORE
UMC 0.13um SP FSG Logic Process high density power-slash core cell library Library_Group 0.13um Bronze
FSD0A_E_POWERSLASH_C
ORE
UMC 90nm SP-RVT lowK process low power standard cell library Library_Group 90nm Bronze
FSD0K_E_POWERSLASH_C
ORE
UMC 90nm LL-RVT LowK Process Low Power PowerSlash Core Cell Library Library_Group 90nm Bronze
FSF0A_ERS_POWERSLASH
_CORE
UMC 55nm SP/RVT Logic Process 7-track PSK cell library Library_Group 55nm Bronze
FSF0F_ERS_POWERSLASH
_CORE
UMC 55nm eFlash/RVT Logic Process 7-track PowerSlash Kit cell library Library_Group 55nm Silver
FSF0L_ERS_POWERSLASH
_CORE
UMC 55nm LP/RVT LowK Logic Process 7-Tracks Powerslash Core Cell Library Library_Group 55nm Silver
FSH0L_ERS_POWERSLASH
_CORE
UMC 40nm LP/RVT LowK Logic Process 7-track PSK Cell Library Library_Group 40nm Silver
FSH0V_DRS_POWERSLASH
_CORE
UMC 40nm HV/RVT Logic Process 7-Track Standard Cell Library (PowerSlash Core) Library_Group 40nm Contact Sales
FSJ0C_DRS_POWERSLASH
_CORE
UMC 28nm HPC/RVT Logic and Mixed-Mode Process 7-track POWERSLASH cell library (C35) Library_Group 28nm Silver
FSJ0C_ERS_POWERSLASH
_CORE
UMC 28nm HPC/RVT Logic and Mixed-Mode Process 7-track POWERSLASH cell library enhanced for routing (C35) Library_Group 28nm Silver
FSJ0L_ERD_POWERSLASH
_CORE
UMC 28nm HLP/RVT Logic and Mixed-Mode Process 7-track Powerslash cell library with LMINUS (C-30 RVT) Library_Group 28nm Contact Sales
 
FSJ0L_ERS_POWERSLASH
_CORE
UMC 28nm HLP/RVT Logic and Mixed-Mode Process 7-track Power Slash Cell Library Library_Group 28nm Silver
FSJ0L_ERU_POWERSLASH
_CORE
UMC 28nm HLP/RVT Logic and Mixed-Mode Process 7-track Powerslash Cell Library with LPLUS (C-38) Library_Group 28nm Contact Sales
 
FSN0U_ERS_POWERSLASH
_CORE
UMC 22nm ULP/RVT Logic and Mixed-Mode Process 7-track POWERSLASH cell library enhanced for routing (C35) Library_Group 22nm Contact Sales
 
 
Logic Libraries > PowerSlash Core Cell Library
> 7-Track > 7T SVT PSK Library 
Cell Name Descriptions Type Process Gradation Literature
FSJ0P_ERS_POWERSLASH
_CORE
UMC 28nm HPC+/SVT Logic and Mixed-Mode Process 7-track POWERSLASH cell library enhanced for routing (C35) Library_Group 28nm Bronze
 
Logic Libraries > PowerSlash Core Cell Library
> 7-Track > 7T uHVT PSK library 
Cell Name Descriptions Type Process Gradation Literature
FSF0G_EHE_POWERSLASH
_CORE
UMC 55nm uLP SST PROCESS uHVT 7-track C60 standard cell powerslash library Library_Group 55nm Bronze
FSF0G_ERE_POWERSLASH
_CORE
UMC 55nm uLP SST PROCESS uHVT 7-track C60 standard cell powerslash library Library_Group 55nm Bronze
FSF0G_EUE_POWERSLASH
_CORE
UMC 55nm uLP SST PROCESS uHVT 7-track C60 standard cell powerslash library Library_Group 55nm Bronze
 
 
Logic Libraries > PowerSlash Core Cell Library
> 8-Track > 8T HVT PSK Library 
Cell Name Descriptions Type Process Gradation Literature
FSE0A_DHM_POWERSLASH
_CORE
UMC 65nm SP-HVT process Power slash cell library Library_Group 65nm Bronze
FSE0K_DHM_POWERSLASH
_CORE
UMC 65nm LL/HVT LowK Logic Process Powerslash core cell library Library_Group 65nm Bronze
FSF0A_DHS_POWERSLASH
_CORE
UMC 55nm SP-HVT LowK Process Power slash Cell Library (8-grid) Library_Group 55nm Bronze
FSF0F_DHS_POWERSLASH
_CORE
UMC 55nm eFlash/HVT LowK Logic Process 8-track POWERSLASH Core Library Library_Group 55nm Silver
FSF0G_DHE_POWERSLASH
_CORE
UMC 55nm uLP SST PROCESS HVT 8-track C60 standard cell Powerslash library Library_Group 55nm Bronze
FSF0L_DHS_POWERSLASH
_CORE
UMC 55nm LP/HVT LowK Logic Process 8-Tracks Powerslash Core Cell Library Library_Group 55nm Silver
FSF0U_DHA_POWERSLASH
_CORE
UMC 55nm ULP/HVT Low-K Logic Process Process 8-track Powerslash Cell Library (C90).W/O deep Nwell. Library_Group 55nm Silver
FSF0U_DHB_POWERSLASH
_CORE
UMC 55nm ULP/HVT Low-K Logic Process Process 8-track Powerslash Cell Library (C60). W/O deep Nwell Library_Group 55nm Silver
FSF0U_DHS_POWERSLASH
_CORE
UMC 55nm ULP/HVT Low-K Logic Process Process 8-track Powerslash Cell Library (C60) w/ Forward Bias. W/ deep Nwell. Library_Group 55nm Silver
FSF0U_DHU_POWERSLASH
_CORE
UMC 55nm ULP/HVT Low-K Logic Process Process 8-track Powerslash Cell Library (C90) w/ Forward Bias. W/ deep Nwell Library_Group 55nm Silver
FSR0F_D_POWERSLASH_C
ORE
UMC 0.11um eFlash/HS Process 8-track generic core cell library Library_Group 0.11um Silver
 
Logic Libraries > PowerSlash Core Cell Library
> 8-Track > 8T LVT PSK Library 
Cell Name Descriptions Type Process Gradation Literature
FSF0F_DLS_POWERSLASH
_CORE
UMC 55nm eFlash/LVT LowK Logic Process 8-track Standard Core Library Library_Group 55nm Silver
FSF0L_DLS_POWERSLASH
_CORE
UMC 55nm LP/LVT LowK Logic Process 8-Tracks Powerslash Core Cell Library Library_Group 55nm Silver
FSF0U_DLS_POWERSLASH
_CORE
UMC 55nm ULP/LVT Low-K Logic Process Process 8-track Powerslash Cell Library (C60) Library_Group 55nm Silver
FSR0P_D_POWERSLASH_C
ORE
UMC 0.11um eFlash/LL Process 8-track cell library Library_Group 0.11um Silver
 
Logic Libraries > PowerSlash Core Cell Library
> 8-Track > 8T RVT PSK Library 
Cell Name Descriptions Type Process Gradation Literature
FSE0A_D_POWERSLASH_C
ORE
UMC 65nm SP/RVT LowK Logic Process Powerlash core cell library Library_Group 65nm Bronze
FSE0K_D_POWERSLASH_C
ORE
UMC 65nm LL-RVT Low-K Process miniLib PowerSlashKit Library_Group 65nm Bronze
FSF0A_DRS_POWERSLASH
_CORE
UMC 55nm SP/RVT LowK Logic Process Powerlash Core Cell Library. Library_Group 55nm Contact Sales
FSF0F_DRS_POWERSLASH
_CORE
UMC 55nm eFlash/RVT LowK Logic Process 8-track PowerSlash Kit cell Library Library_Group 55nm Silver
FSF0L_DRS_POWERSLASH
_CORE
UMC 55nm LP/RVT LowK Logic Process 8-Tracks Powerslash Core Cell Library Library_Group 55nm Silver
FSF0U_DRS_POWERSLASH
_CORE
UMC 55nm ULP/RVT Low-K Logic Process Process 8-track Powerslash Cell Library (C60) Library_Group 55nm Silver
 
Logic Libraries > PowerSlash Core Cell Library
> 8-Track > 8T uHVT PSK Library 
Cell Name Descriptions Type Process Gradation Literature
FSF0G_DUU_POWERSLASH
_CORE
UMC 55nm uLP SST PROCESS uHVT 8-track C90 standard cell powerslash library Library_Group 55nm Bronze
FSF0U_DUU_POWERSLASH
_CORE
UMC 55nm ULP/uHVT Low-K Logic Process Process 8-track Powerslash Cell Library (C90) w/ Forward Bias. W/ deep Nwell. Library_Group 55nm Bronze
 
Logic Libraries > PowerSlash Core Cell Library
> 9-Track 
Cell Name Descriptions Type Process Gradation Literature
FSH0L_AHS_POWERSLASH
_CORE
UMC 40nm LP/HVT LowK Logic Process 9-track Power Slash Cell Library Library_Group 40nm Bronze
FSH0L_ALS_POWERSLASH
_CORE
UMC 40nm LP/LVT LowK Logic Process 9-track Power Slash Cell Library Library_Group 40nm Bronze
FSH0L_ARS_POWERSLASH
_CORE
UMC 40nm LP/RVT LowK Logic Process 9-track Power Slash Cell Library Library_Group 40nm Bronze
FSJ0C_ALS_POWERSLASH
_CORE
UMC 28nm HPC/LVT Logic and Mixed-Mode Process 9-track PowerSlash core cell library (C35) Library_Group 28nm Bronze
FSJ0C_ARS_POWERSLASH
_CORE
UMC 28nm HPC/RVT Logic and Mixed-Mode Process 9-track PowerSlash core cell library (C35) Library_Group 28nm Bronze
 
Logic Libraries > PowerSlash Core Cell Library
> 9-Track > 9T HVT PSK Library 
Cell Name Descriptions Type Process Gradation Literature
FSH0L_BHS_POWERSLASH
_CORE
UMC 40nm LP/HVT Logic Process 9-Track Standard Cell Library (PowerSlash Core) Library_Group 40nm Silver
FSH0L_XHS_POWERSLASH
_CORE
UMC 40nm LP/HVT Logic Process SYNS-like 9T POWERSLASH Cell Library Library_Group 40nm Contact Sales
 
FSH0V_AHS_POWERSLASH
_CORE
UMC 40nm HV/HVT Logic Process 9-Track Standard Cell Library (PowerSlash Core) Library_Group 40nm Bronze
FSJ0C_CHS_POWERSLASH
_CORE
UMC 28nm HPC/HVT Logic and Mixed-Mode Process 9-track POWERSLASH cell library enhanced for routing (C35) Library_Group 28nm Bronze
FSJ0L_BHS_POWERSLASH
_CORE
UMC 28nm HLP/HVT Logic Process 9-track POWERSLASH_CORE core cell library Library_Group 28nm Silver
FSJ0L_CHS_POWERSLASH
_CORE
UMC 28nm HLP/HVT Logic and Mixed-Mode Process 9-track M1+ (C35) powerslash cell library Library_Group 28nm Bronze
FSJ0P_CHS_POWERSLASH
_CORE
UMC 28nm Logic/Mixed-Mode HPC+ Process 9 track HVT C35 Powerslash cell library Library_Group 28nm Contact Sales
 
FSN0U_CHS_POWERSLASH
_CORE
UMC 22nm ULP/HVT Logic and Mixed-Mode Process 9-track Powerslash cell library enhanced for routing (C35) Library_Group 22nm Contact Sales
 
FSN0U_CRS_POWERSLASH
_CORE
UMC 22nm ULP/HVT Logic and Mixed-Mode Process 9-track POWERSLASH cell library enhanced for routing (C35) Library_Group 22nm Contact Sales
 
 
Logic Libraries > PowerSlash Core Cell Library
> 9-Track > 9T LVT PSK Library 
Cell Name Descriptions Type Process Gradation Literature
FSH0L_BLS_POWERSLASH
_CORE
UMC 40nm LP/LVT Logic Process 9-Track Standard Cell Library (PowerSlash Core) Library_Group 40nm Silver
FSH0L_XLS_POWERSLASH
_CORE
UMC 40nm LP/LVT Logic Process SYNS-like 9T POWERSLASH Cell Library Library_Group 40nm Contact Sales
 
FSH0V_ALS_POWERSLASH
_CORE
UMC 40nm HV/LVT Logic Process 9-Track Standard Cell Library (PowerSlash Core) Library_Group 40nm Bronze
FSJ0C_CLS_POWERSLASH
_CORE
UMC 28nm HPC/LVT Logic and Mixed-Mode Process 9-track POWERSLASH cell library enhanced for routing (C35) Library_Group 28nm Bronze
 
FSJ0L_BLS_POWERSLASH
_CORE
UMC 28nm HLP/LVT Logic Process 9-track Powerslash standard core cell library (C35) Library_Group 28nm Silver
FSJ0L_CLS_POWERSLASH
_CORE
UMC 28nm HLP/LVT Logic and Mixed-Mode Process 9-track M1+ (C35) powerslash cell library Library_Group 28nm Bronze
 
FSJ0P_CLS_POWERSLASH
_CORE
UMC 28nm Logic/Mixed-Mode HPC+ Process 9 track LVT C35 Powerslash cell library Library_Group 28nm Contact Sales
 
FSN0U_CLS_POWERSLASH
_CORE
UMC 22nm ULP/LVT Logic and Mixed-Mode Process 9-track POWERSLASH cell library enhanced for routing (C35) Library_Group 22nm Contact Sales
 
 
Logic Libraries > PowerSlash Core Cell Library
> 9-Track > 9T RVT PSK Library 
Cell Name Descriptions Type Process Gradation Literature
FSH0L_BRS_POWERSLASH
_CORE
UMC 40nm LP/RVT Logic Process 9-Track Standard Cell Library (PowerSlash Core) Library_Group 40nm Silver
FSH0L_XRS_POWERSLASH
_CORE
UMC 40nm LP/RVT Logic Process SYNS-like 9T POWERSLASH Cell Library Library_Group 40nm Contact Sales
 
FSH0V_ARS_POWERSLASH
_CORE
UMC 40nm HV/RVT Logic Process 9-Track Standard Cell Library (PowerSlash Core) Library_Group 40nm Bronze
FSJ0C_CRS_POWERSLASH
_CORE
UMC 28nm HPC/RVT Logic and Mixed-Mode Process 9-track POWERSLASH cell library enhanced for routing (C35) Library_Group 28nm Bronze
FSJ0L_BRS_POWERSLASH
_CORE
UMC 28nm Logic and Mixed-Mode HLP/RVT Process 9-track PowerSlash cell library (C35) Library_Group 28nm Silver
FSJ0L_CRS_POWERSLASH
_CORE
UMC 28nm HLP/RVT Logic and Mixed-Mode Process 9-track M1+ (C35) powerslash cell library Library_Group 28nm Bronze
FSJ0P_CRS_POWERSLASH
_CORE
UMC 28nm Logic/Mixed-Mode HPC+ Process 9 track RVT C35 Powerslash cell library Library_Group 28nm Contact Sales