Interface Solution

Updated On:2018-07-22
Gradation
Faraday IPs are rated according to the IPs’ maturity and customer acceptance. They are graded by the rules described as below,


Platinum P Five (5) productions verified
Gold G Mass production proven
Silver S Silicon proven, Formal release
Silver Minus S- Manufacturing onging
Bronze B Pre-Silicon release
 
Interface Solution > Automotive IPs
> CAN Controller 
Cell Name Descriptions Type Process Gradation Literature
FTCAN2 CAN Bus Controller. Supports A/B/Flexible Data-Rate. Soft_IP Contact Sales
 
 
Interface Solution > Automotive IPs
> DSI Controller 
Cell Name Descriptions Type Process Gradation Literature
FTDSIM300 FTDSIM300 DSI3.0 (distributed system interface) Master Soft_IP Contact Sales
 
FTDSIS300 DSI3.0 (distributed system interface) slave Soft_IP Contact Sales
 
 
Interface Solution > DDR
 
Cell Name Descriptions Type Process Gradation Literature
FXDDR3A110NSHJ0C DDR3 RTL Digitalize PHY AC block and AIO block; UMC 28nm HPC/RVT Logic Process using FSJ0C_ARS Analog_IP 28nm Contact Sales
 
FXDDR3A50225EWHJ0L Command/Address Block of DDR3/DDR3L/DDR2/LPDDR2/LPDDR Combo PHY Horizontal version; UMC 28nm HLP Logic and Mixed-Mode Process Analog_IP 28nm Contact Sales
FXDDR3A50225NSHJ0L Command/Address Block of DDR3/DDR3L/DDR2/LPDDR2/LPDDR Combo PHY Vertical version; UMC 28nm HLP Logic and Mixed-Mode Process Analog_IP 28nm Contact Sales
FXDDR3D110NSHJ0C DDR3 RTL Digitalize PHY DAT block and DIO block; UMC 28nm HPC/RVT Logic Process using FSJ0C_ARS Analog_IP 28nm Contact Sales
 
FXDDR3D50225EWHJ0L Data Block of DDR3/DDR3L/DDR2/LPDDR2/LPDDR Combo PHY Horizontal version; UMC 28nm HLP Logic and Mixed-Mode Process Analog_IP 28nm Contact Sales
FXDDR3D50225NSHJ0L Data Block of DDR3/DDR3L/DDR2/LPDDR2/LPDDR Combo PHY Vertical version; UMC 28nm HLP Logic and Mixed-Mode Process Analog_IP 28nm Contact Sales
 
Interface Solution > DDR
> DDR Controller > DDR3 - Addresss/Command  
Cell Name Descriptions Type Process Gradation Literature
FXDDR3PHYA100EWHJ0C DDR3 RTL Digitalize PHY AC block; UMC 28nm HPC/RVT Logic Process using FSJ0C_ARS Analog_IP 28nm Contact Sales
FXDDR3PHYA100NSHJ0C DDR3 RTL Digitalize PHY AC block; UMC 28nm HPC/RVT Logic Process using FSJ0C_ARS Analog_IP 28nm Contact Sales
 
 
Interface Solution > DDR
> DDR Controller > DDR3 - Data Block 
Cell Name Descriptions Type Process Gradation Literature
FXDDR3PHYD100EWHJ0C DDR3 RTL Digitalize PHY DATA block; UMC 28nm HPC/RVT Logic Process using FSJ0C_ARS Analog_IP 28nm Contact Sales
 
FXDDR3PHYD100NSHJ0C DDR3 RTL Digitalize PHY DATA block; UMC 28nm HPC/RVT Logic Process using FSJ0C_ARS Analog_IP 28nm Contact Sales
 
Interface Solution > DDR
> DDR IO > DDR1 - SSTL2 IO Library 
Cell Name Descriptions Type Process Gradation Literature
FOA0A_A33_TMVH33L25_
SSTL2C1WLVTTL_IO
UMC 0.18um GII Logic Process SSTL2 ClassI with 3.3V LVTTL combo IO Cell Library Library_Group 0.18um Silver
 
FOA0A_A33_TMVH33L25_
SSTL2C2WLVTTL_IO
UMC 0.18um GII Logic Process SSTL2 ClassII IO group with 3.3V LVTTL combo IO Cell Library Library_Group 0.18um Silver
FOA0A_O_TMVH33L25_SS
TL2C1WLVTTL_IO
UMC 0.18um GII Logic Process 2.5/3.3V SSTL2 ClassI/LVTTL combo IO with POC solution Library_Group 0.18um Silver
FOA0A_O_TMVH33L25_SS
TL2C2WLVTTL_IO
UMC 0.18um GII Logic Process 2.5V/3.3V SSTL2 Class II/LVTTL combo IO with POC solution Library_Group 0.18um Silver
FOC0H_A33_TMVH33L25_
SSTL2C1WLVTTL_IO
UMC 0.13um process,SSTL-2 (ClassI)/LVTTL (10mA) Combo I/O Cells; This IP is branched from 'FSC0H_D_TMVH33L25_SSTL2C1WLVTTL_IO'. Library_Group 0.13um Silver
FOC0H_A33_TMVH33L25_
SSTL2C2WLVTTL_IO
UMC 0.13um Logic Process,Specification for SSTL-2 Class-II and LVTTL Combo IO; This IP is branched from 'FSC0H_D_TMVH33L25_SSTL2C2WLVTTL_IO' Library_Group 0.13um Silver
FOC0H_B33_TMVH33VL25
V_SSTL2C1WLVTTL_IO
UMC 0.13um HS/FSG Logic Process Ultra-slim SSTL-2 (ClassI)/LVTTL (10mA) Combo I/O Cells Library_Group 0.13um Contact Sales
 
FOC0H_O33_TMVH33L25_
SSTL2C1WLVTT
UMC 0.13um HS/FSG SSTL2 (class 1) IO for BOAC Library_Group 0.13um Silver
FOC0H_O33_TMVH33L25_
SSTL2C2WLVTT
UMC 0.13um HS/FSG Logic Process 2.5V/3.3V SSTL2-Class II/LVTTL combo IO with POC solution Library_Group 0.13um Silver
FOC0H_P33_T25_SSTL2C
1_IO
UMC 0.13um HS/FSG Logic Process SSTL-2 (ClassI) mini BOAC I/O Cells Library_Group 0.13um Bronze
FOD0A_O25_T25_SSTL2C
1_IO
UMC 90nm SP/Low-K Logic Process SSTL-2 (ClassI) BOAC I/O Cells Library_Group 90nm Bronze
 
FOR0B_O33_TMVH25L18_
SSTL2WMDDR_IO
UMC 0.11um AE/HS Logic Process DD1/DDR2 combo MDDR IO Cell Library Library_Group 0.11um Bronze
FS90A_B_T25_SSTL2_IO UMC 0.25um LOGIC process true 2.5V SSTL-2 IO cells Library_Group 0.25um Silver
 
FS90A_B_TMVH33L25_SS
TL2C1WLVTTL_IO
UMC 0.25um process SSTL2 ClassI with 3.3V LVTTL combo. Library_Group 0.25um Silver
 
FSA0A_C_T25_SSTL2_IO UMC 0.18um GII process true 2.5V SSTL-2 IO cells Library_Group 0.18um Silver
FSA0A_C_TMVH33L25_SS
TL2C1WLVTTL_IO
UMC 0.18um process SSTL2 ClassI with 3.3V LVTTL combo Library_Group 0.18um Silver
FSA0A_C_TMVH33L25_SS
TL2C2WLVTTL_IO
UMC 0.18um process ,SSTL2 ClassII IO group with 3.3V LVTTL combo. Library_Group 0.18um Silver
FSB0G_A_TMVH33L25_SS
TL2C2WLVTTL_IO
UMC 0.15um SP process standard Multi-Voltage High 3.3V Low 2.5V SSTL-2 class-II with LVTTL IO cells. Library_Group 0.15um Silver
 
Interface Solution > DDR
> DDR IO > DDR2 - SSTL18 IO Library 
Cell Name Descriptions Type Process Gradation Literature
FOC0H_O33_TMVH25L18_
SSTL18AWSSTL2C1_IO
UMC, 0.13um Logic HS/FSG process SSTL(2.5V) & SSTL18 (1.8V) combo IO Library_Group 0.13um Bronze
 
FOD0A_B25_T18_SSTL18
AWLVCMOS18_IO
UMC 90nm SP RVT process SSTL18 IO cell library Library_Group 90nm Contact Sales
 
FOF0L_PRS25_TMVH25L1
8_SSTL2WPWL_IO
55LP DDR1/DDR2 IO. 1. U55 LP Process 2. DDR2/DDR1 IO -2.5V SSTL2/1.8 SSTl18 ( CMOS/SSTL) –4 Driving strength @ Target: DDR 533 Mbps( IO 266 MHz) -VCCK Core power-off, All IO pull low Library_Group 55nm Bronze
FOH0L_QRS25_T18_SSTL
18A_IO
40LP DDR3 IO PG lib IP (characterized voltage: 1.8V). Library_Group 40nm Contact Sales
 
 
Interface Solution > DDR
> DDR IO > DDR3 - POD IO 
Cell Name Descriptions Type Process Gradation Literature
FOJ0L_QRS25_T15_DDR3
WPOD_IO
UMC 28nm HLP/RVT Low-K Logic process true 1.5V DDR3 with 2.5V Device IO cell Library Library_Group 28nm Contact Sales
 
 
Interface Solution > DDR
> DDR IO > MDDR IO Library 
Cell Name Descriptions Type Process Gradation Literature
FOC0H_A33_T18_MDDR_I
O
UMC 0.13um HS/FSG Process High speed 1.2/3.3V Process Mobil DDR IO Group Library_Group 0.13um Bronze
FOC0H_O33_T18_MDDR_I
O
UMC 0.13um HS/FSG Logic Library (core) 1.8V MDDR IO with POC solution Library_Group 0.13um Bronze
FOD0K_B25_T18_MDDR_B
_IO
UMC 90nm Logic LL-RVT process 2.5V standard IO cell Library (Version B MDDR IO) Library_Group 90nm Silver
 
Interface Solution > DDR
> DDR PHY - Combo > DDR3/3L - Combo Block 
Cell Name Descriptions Type Process Gradation Literature
FXDDR3LTA102HH0L DDR3/DDR3L/LPDDR2 combo PHY ( not support DDR3 leveling function), command / address block,UMC 40nm LP/RVT LowK Logic Process. Analog_IP 40nm Contact Sales
 
 
Interface Solution > DDR
> DDR PHY - Command/Address > DDR1 - Command/Address 
Cell Name Descriptions Type Process Gradation Literature
FXDDR1A173HF0A DDR1/MDDR PHY CMD/ADDR BLOCK ; UMC 55nm SP/RVT with 2.5V device LowK Logic Process Analog_IP 55nm Bronze
 
 
Interface Solution > DDR
> DDR PHY - Command/Address > DDR2 - Command/Address 
Cell Name Descriptions Type Process Gradation Literature
FXDDR2A173HE0A DDR2/MDDR PHY CMD/ADDR BLOCK ; UMC 65nm 1.0V process with 2.5V device SP/RVT Lowk Logic Process Analog_IP 65nm Silver
FXDDR2A173HF0A DDR2/MDDR Combo PHY CMD ADDR block ; UMC 55nm SP/RVT Lowk Process with 2.5V device Analog_IP 55nm Silver
FXDDR2A174HE0A DDR2/MDDR PHY CMD/ADDR BLOCK for DIMM usage ; UMC 65nm 1.0V with 2.5V Device SP/RVT LowK Logic Process Analog_IP 65nm Silver
FXDDR2A174HF0A DDR2/MDDR PHY CMD/ADDR BLOCK for DIMM usage; UMC 55nm 1.0V with 2.5V device SP/RVT LowK Logic Process Analog_IP 55nm Silver
FXDDR2A200HC0H DDR2/MDDR Combo Command/Address Block ; UMC 0.13um HS/FSG Logic Process Analog_IP 0.13um Bronze
FXDDR2A200HE0L DDR2/DDR1/MDDR Combo Command/Address Block ; UMC 65nm LP/RVT LowK Logic Process Analog_IP 65nm Silver
FXDDR2A200HR0B Command/address block of 1:2 DDR2-PHY ; 0.11um HS/AE (AL Advanced Enhancement) Logic Process Analog_IP 0.11um Silver Minus
FXDDR2A200HR0H 1:2 DDR2/DDR1/MDDR combo PHY; UMC 0.11um HS/Cu Logic Process Analog_IP 0.11um Silver
 
FXDDRIIA171HC0H DDR2 PHY Command/Address Block ; UMC 0.13um HS/FSG Logic Process Analog_IP 0.13um Platinum
FXDDRIIA172HC0H DDR2 PHY Command/Address Block (for Chip Application); UMC 0.13um HS/FSG Logic Process Analog_IP 0.13um Silver
FXDDRIIA173HD0A_FTC DDR2-PHY command/address block for DRAM chip, BOAC ; UMC 90nm SP/RVT Low-K Logic Process Analog_IP 90nm Silver Minus
FXDDRIIA174HD0A DDR2-PHY Command/Address block; UMC 90nm SP/RVT Lowk Process Analog_IP 90nm Gold
 
Interface Solution > DDR
> DDR PHY - Command/Address > DDR3 PHY - Command/Address 
Cell Name Descriptions Type Process Gradation Literature
FXDDR3AIO502EWHJ0C_F
TC
IO Command/Address Block of DDR3/DDR3L/DDR2/LPDDR2/LPDDR ; UMC 28nm HPC/RVT Logic Process Analog_IP 28nm Contact Sales
 
FXDDR4AFC602HH0L Command/Address Block of DDR3/DDR4/LPDDR2/LPDDR3 Combo PHY for Solder bump Flip chip version ; UMC 40nm LP LowK Logic Process Analog_IP 40nm Contact Sales
 
 
Interface Solution > DDR
> DDR PHY - Command/Address > DDR3/3L - Command/Address 
Cell Name Descriptions Type Process Gradation Literature
FXDDR3A100HD0A DDR2/3 Combo Command /Address Block (with 2.5V IO device) ; UMC 90nm SP-RVT LowK Logic Process Analog_IP 90nm Silver Minus
FXDDR3A100HH0L DDR23 COMBO PHY CMD/ADDR BLOCK ; UMC 40LP/RVT LowK Logic Process with 2.5V device Analog_IP 40nm Silver
FXDDR3A300HF0A Command/Address Block of DDR3 Combo PHY for DIMM version ; UMC 55nm SP/RVT LowK Logic Process Analog_IP 55nm Silver
FXDDR3A300HF0L Command/Address Block of DDR3 Combo PHY for DIMM version ; UMC 55nm LP/RVT LowK Logic Process Analog_IP 55nm Silver Minus
FXDDR3A402HF0A Command/Address Block of DDR3/DDR3L/DDR2/LPDDR2/LPDDR Combo PHY for Chip Application; UMC 55nm SP/RVT LowK Logic Process Analog_IP 55nm Silver
FXDDR3A403HF0A Command/Address Block of DDR3/DDR3L/DDR2/LPDDR2/LPDDR Combo PHY for Chip Application;UMC 55nm SP/RVT LowK PROCESS. Analog_IP 55nm Silver
FXDDR3A412HF0L Command/Address Block of DDR3/DDR3L/DDR2/LPDDR2/LPDDR Combo PHY for Chip Application; UMC 55nm LP/RVT LowK Logic Process Analog_IP 55nm Bronze
FXDDR3A502HF0A Command/Address Block of DDR3/DDR3L/DDR2/LPDDR2/LPDDR Combo PHY for Chip Application (compliant to DFI); UMC 55nm SP/RVT LowK Logic Process Analog_IP 55nm Contact Sales
 
FXDDR3A502HH0L Command/Address Block of DDR3/DDR3L/DDR2/LPDDR2/LPDDR Combo PHY for Chip Application (compliant with DFI spec); UMC 40nm LP LowK Logic Process Analog_IP 40nm Silver
FXDDR3A503HH0L DDR3 Combo PHY COMM/ADDR Block for 2-rank and solder bump application; UMC 40nm LP/RVT Logic Process Analog_IP 40nm Contact Sales
 
FXDDR3AFC502HH0L DDR3 Combo PHY COMM/ADDR Block for 2-rank and solder bump application; UMC 40nm LP/RVT Logic Process Analog_IP 40nm Contact Sales
 
 
Interface Solution > DDR
> DDR PHY - Command/Address > DDR4 - Command/Address 
Cell Name Descriptions Type Process Gradation Literature
FXDDR4AFC101HH0L DDR34 COMBO PHY ADDR Block for Solder bump Flip chip version ;UMC 40nm LP/RVT Logic Process Analog_IP 40nm Contact Sales
 
FXDDR4AFD612EWHJ0C Command/Address Block of DDR3/DDR4/LPDDR2/LPDDR3 Combo PHY supporting 2-rank application for Copper Pillar Bump Flip Chip Version ; UMC 28nm Logic and Mixed-Mode Low-K HPC Process Analog_IP 28nm Contact Sales
 
FXDDR4AFD612HH0L Command/Address Block of DDR3/DDR4/LPDDR2/LPDDR3 Combo PHY supporting 2-rank application for Copper Pillar Bump Flip Chip Version; UMC 40nm LP LVT/RVT LowK Logic Process Analog_IP 40nm Contact Sales
FXDDR4AFD612NSHJ0C Command/Address Block of DDR3/DDR4/LPDDR2/LPDDR3 Combo PHY supporting 2-rank application for Copper Pillar Bump Flip Chip Version ; UMC 28nm Logic and Mixed-Mode Low-K HPC Process Analog_IP 28nm Contact Sales
 
 
Interface Solution > DDR
> DDR PHY - Command/Address > LPDDR2 - Command/Address 
Cell Name Descriptions Type Process Gradation Literature
FXDDR3A412HF0A Command/Address Block of DDR3/DDR3L/DDR2/LPDDR2/LPDDR Combo PHY for Chip Application; UMC 55nm SP/RVT LowK Logic Process Analog_IP 55nm Bronze
FXLPDDR2A102HH0L_SIP 40nm LPDDR2-PHY command/address block for SIP Analog_IP 40nm Contact Sales
 
 
Interface Solution > DDR
> DDR PHY - Command/Address > LPDDR3 - Command/Address 
Cell Name Descriptions Type Process Gradation Literature
FXDDR4AFD612EWHJ0P Command/Address Block of DDR3/DDR4/LPDDR2/LPDDR3 Combo PHY supporting 2-rank application for Copper Pillar Bump Flip Chip Version ; UMC 28nm Logic and Mixed-Mode Low-K HPC+ Process Analog_IP 28nm Contact Sales
 
FXDDR4AFD612NSHJ0P Command/Address Block of DDR3/DDR4/LPDDR2/LPDDR3 Combo PHY supporting 2-rank application for Copper Pillar Bump Flip Chip Version ; UMC 28nm Logic and Mixed-Mode Low-K HPC+ Process Analog_IP 28nm Contact Sales
 
FXDDR4AFD622EWHJ0P Command/Address Block of DDR3/DDR4/LPDDR2/LPDDR3 Combo PHY supporting 2-rank application for Copper Pillar Bump Flip Chip Version ; UMC 28nm Logic and Mixed-Mode Low-K HPC+ Process Analog_IP 28nm Contact Sales
 
FXDDR4AFD622NSHJ0P Command/Address Block of DDR3/DDR4/LPDDR2/LPDDR3 Combo PHY supporting 2-rank application for Copper Pillar Bump Flip Chip Version ; UMC 28nm Logic and Mixed-Mode Low-K HPC+ Process Analog_IP 28nm Contact Sales
 
FXLPDDR3AW101HH0L LPDDR3-PHY Command/address block for LightCo ; UMC 40nm LP/RVT Logic Process Analog_IP 40nm Contact Sales
 
 
Interface Solution > DDR
> DDR PHY - Compensation > DDR2 - Compensation 
Cell Name Descriptions Type Process Gradation Literature
FXDDR2COMP010HE0A DDR2 PHY compensation block; UMC 65nm SP/RVT LowK Logic Process Analog_IP 65nm Silver
FXDDR2COMP010HE0A DDR2 PHY compensation block; UMC 65nm SP/RVT LowK Logic Process Analog_IP 65nm Silver
FXDDR2COMP010HF0A DDR2 PHY Compensation block; UMC 55nm SP/RVT LowK Logic Process Analog_IP 55nm Silver
FXDDR2COMP010HF0A DDR2 PHY Compensation block; UMC 55nm SP/RVT LowK Logic Process Analog_IP 55nm Silver
FXDDR2COMP011HC0H DDR2 PHY compensation block for 171 series (non BOAC); UMC 0.13um HS/FSG Logic Process Analog_IP 0.13um Silver
FXDDR2COMP012HC0H DDR2-PHY compensation block, BOAC; UMC 0.13um HS/FSG process Analog_IP 0.13um Silver
FXDDR2COMP012HC0H DDR2-PHY compensation block, BOAC; UMC 0.13um HS/FSG process Analog_IP 0.13um Silver
FXDDR2COMP013HD0A_FT
C
DDR2-PHY compensation block, BOAC; UMC 90nm SP/RVT Low-K Logic process Analog_IP 90nm Platinum
FXDDR2COMP013HD0A_FT
C
DDR2-PHY compensation block, BOAC; UMC 90nm SP/RVT Low-K Logic process Analog_IP 90nm Platinum
 
Interface Solution > DDR
> DDR PHY - Compensation > DDR3/3L - Compensation 
Cell Name Descriptions Type Process Gradation Literature
FXDDR3COMP100HD0A DDR2/3 COMBO Compensation block (2.5V IO device) ; UMC 90nm SP-RVT LowK Logic Porcess Analog_IP 90nm Silver
FXDDR3COMP100HH0L DDR23 COMBO PHY compensation Block ; UMC 40LP/RVT LowK Logic Process with 2.5V device Analog_IP 40nm Silver
FXDDR3COMP300HF0A Compensation Block of DDR3 Combo PHY for DIMM version ; UMC 55nm SP/RVT LowK Logic Process Analog_IP 55nm Silver
FXDDR3COMP300HF0A Compensation Block of DDR3 Combo PHY for DIMM version ; UMC 55nm SP/RVT LowK Logic Process Analog_IP 55nm Silver
FXDDR3COMP300HF0L Compensation Block of DDR3 Combo PHY for DIMM version ; UMC 55nm LP/RVT LowK Logic Process Analog_IP 55nm Silver Minus
FXDDR3COMP400HF0A Compensation Block of DDR3/DDR3L/DDR2/LPDDR2/LPDDR Combo PHY; UMC 55nm SP/RVT LowK Logic Process Analog_IP 55nm Silver
FXDDR3COMP400HF0A Compensation Block of DDR3/DDR3L/DDR2/LPDDR2/LPDDR Combo PHY; UMC 55nm SP/RVT LowK Logic Process Analog_IP 55nm Silver
FXDDR3COMP400HF0A Compensation Block of DDR3/DDR3L/DDR2/LPDDR2/LPDDR Combo PHY; UMC 55nm SP/RVT LowK Logic Process Analog_IP 55nm Silver
FXDDR3COMP400HF0L Compensation Block of DDR3/DDR3L/DDR2/LPDDR2/LPDDR Combo PHY; UMC 55nm LP/RVT LowK Logic Process Analog_IP 55nm Bronze
FXDDR3COMP502HJ0C Compensation Block of DDR3/DDR3L/DDR2/LPDDR2/LPDDR Combo PHY for SIP Application; UMC 28nm HPC/RVT LowK Logic Process Analog_IP 28nm Contact Sales
FXDDR3COMP502NSHJ0C Compensation Block of DDR3/DDR3L/DDR2/LPDDR2/LPDDR Combo PHY for SIP Application; UMC 28nm HPC/RVT LowK Logic Process; Vertical version Analog_IP 28nm Contact Sales
 
FXDDR3COMPFC502HH0L DDR3 Combo PHY Compensation Block for solder bump application; UMC 40nm LP/RVT Logic Process Analog_IP 40nm Contact Sales
 
FXDDR3LTCOMP100HH0L compensation block for FXDDR3LTA102HH0L and FXDDR3LTD102HH0L,UMC 40nm LP/RVT LowK Logic Process . Analog_IP 40nm Silver
FXDDR3LTCOMP100HH0L compensation block for FXDDR3LTA102HH0L and FXDDR3LTD102HH0L,UMC 40nm LP/RVT LowK Logic Process . Analog_IP 40nm Silver
FXDDR3LTCOMP100HH0L compensation block for FXDDR3LTA102HH0L and FXDDR3LTD102HH0L,UMC 40nm LP/RVT LowK Logic Process . Analog_IP 40nm Silver
FXDDR3LTCOMP100HH0L compensation block for FXDDR3LTA102HH0L and FXDDR3LTD102HH0L,UMC 40nm LP/RVT LowK Logic Process . Analog_IP 40nm Silver
 
Interface Solution > DDR
> DDR PHY - Compensation > DDR4 - Compensation 
Cell Name Descriptions Type Process Gradation Literature
FXDDR4COMP101HH0L UMC 40nm LP process DDR34/LPDDR23 COMPENSATION Block with 2.5V Device Analog_IP 40nm Contact Sales
FXDDR4COMPFD612EWHJ0
P
Compensation Block of DDR3/DDR4/LPDDR2/LPDDR3 Combo PHY for Copper Pillar Bump Flip Chip Version ; UMC 28nm Logic and Mixed-Mode Low-K HPC+ Process Analog_IP 28nm Contact Sales
 
FXDDR4COMPFD612NSHJ0
P
Compensation Block of DDR3/DDR4/LPDDR2/LPDDR3 Combo PHY for Copper Pillar Bump Flip Chip Version ; UMC 28nm Logic and Mixed-Mode Low-K HPC+ Process Analog_IP 28nm Contact Sales
 
 
Interface Solution > DDR
> DDR PHY - Compensation > LPDDR2 - Compensation 
Cell Name Descriptions Type Process Gradation Literature
FXDDR3COMP50225EWHJ0
L
Compensation Block of DDR3/DDR3L/DDR2/LPDDR2/LPDDR Combo PHY; UMC 28nm HLP/RVT LowK Logic Process; Horizontal version Analog_IP 28nm Contact Sales
FXDDR3COMP50225NSHJ0
L
Compensation Block of DDR3/DDR3L/DDR2/LPDDR2/LPDDR Combo PHY; UMC 28nm HLP/RVT LowK Logic Process; Vertical version Analog_IP 28nm Contact Sales
 
Interface Solution > DDR
> DDR PHY - Data Block > DDR1 - Data Block 
Cell Name Descriptions Type Process Gradation Literature
FXDDR1D173HF0A DDR1/MDDR PHY Data block ; UMC 55nm SP/RVT with 2.5V device LowK Logic Process Analog_IP 55nm Bronze
 
 
Interface Solution > DDR
> DDR PHY - Data Block > DDR2 - Data Block 
Cell Name Descriptions Type Process Gradation Literature
FXDDR2D172HR0B DDRII Data Block for Chip Application; UMC 0.11um HS/AE (AL Advance Enhancement) Logic Process Analog_IP 0.11um Bronze
 
FXDDR2D173HE0A DDR2/MDDR Combo PHY for Chip load usage ; UMC 65NM SP-RVT with 2.5V device LowK Logic Process Analog_IP 65nm Bronze
FXDDR2D173HF0A DDR2/MDDR COMBO PHY Data block for Chip usage ; UMC 55nm SP/RVT with 2.5V device LowK Logic Process Analog_IP 55nm Silver
FXDDR2D174HE0A DDR2/MDDR PHY Data block ; UMC 65nm 1.0V with 2.5V device SP/RVT LowK Logic Process Analog_IP 65nm Silver
FXDDR2D174HF0A DDR2/MDDR Combo PHY data block ; UMC 55nm SP process with 2.5V device Analog_IP 55nm Silver
FXDDR2D200HC0H DDR2/MDDR Combo Data Block ; 0.13um Logic HS/FSG Logic Process Analog_IP 0.13um Bronze
FXDDR2D200HE0L DDR2/DDR1/MDDR Combo Data Block ; UMC 65nm LP/RVT LowK Logic Process Analog_IP 65nm Silver
FXDDR2D200HR0B Data block of 1:2 DDR2-PHY ; UMC 0.11um HS/AE (AL Advanced Enhancement) Logic Process Analog_IP 0.11um Silver Minus
FXDDR2D200HR0H 1:2 DDR2/DDR1/MDDR combo PHY; UMC 0.11um HS/Cu Logic Process Analog_IP 0.11um Silver
 
FXDDRIID171HC0H DDR2 PHY Data Block ;UMC 0.13um Logic HS/FSG Process Analog_IP 0.13um Gold
FXDDRIID172HC0H DDRII Data Block for Chip Application; UMC 0.13um HS/FSG Logic Process Analog_IP 0.13um Silver
FXDDRIID173HD0A_FTC DDR2-PHY data block with BOAC IO; UMC 90nm SP/RVT Lowk Logic Process Analog_IP 90nm Silver Minus
FXDDRIID174HD0A DDR2-PHY data block; UMC 90nm SP/RVT Lowk Process Analog_IP 90nm Gold
 
Interface Solution > DDR
> DDR PHY - Data Block > DDR3 PHY - Data Block 
Cell Name Descriptions Type Process Gradation Literature
FXDDR3DIO502NSHJ0C_F
TC
IO Data Block of DDR3/DDR3L/DDR2/LPDDR2/LPDDR ; UMC 28nm HPC/RVT Logic Process Analog_IP 28nm Contact Sales
 
 
Interface Solution > DDR
> DDR PHY - Data Block > DDR3/3L - Data Block 
Cell Name Descriptions Type Process Gradation Literature
FXDDR3D100HD0A DDR2/3 PHY Combo PHY data block (1.0v SP & 2.5V device); UMC 90nm SP/RVT LowK Logic Process Analog_IP 90nm Silver
FXDDR3D100HH0L DDR23 COMBO PHY Data Block ; UMC 40nm LP/RVT LowK Logic Process with 2.5V device Analog_IP 40nm Silver
FXDDR3D300HF0A Data Block of DDR3 Combo PHY for DIMM version ; UMC 55nm SP/RVT LowK Logic Process Analog_IP 55nm Silver
FXDDR3D300HF0A Data Block of DDR3 Combo PHY for DIMM version ; UMC 55nm SP/RVT LowK Logic Process Analog_IP 55nm Silver
FXDDR3D300HF0L Data Block of DDR3 Combo PHY for DIMM version ; UMC 55nm LP/RVT LowK Logic Process Analog_IP 55nm Silver Minus
FXDDR3D402HF0A Data Block of DDR3/DDR3L/DDR2/LPDDR2/LPDDR Combo PHY for Chip Application; UMC 55nm SP/RVT LowK Logic Process Analog_IP 55nm Silver
FXDDR3D402HF0A Data Block of DDR3/DDR3L/DDR2/LPDDR2/LPDDR Combo PHY for Chip Application; UMC 55nm SP/RVT LowK Logic Process Analog_IP 55nm Silver
FXDDR3D412HF0L Data Block of DDR3/DDR3L/DDR2/LPDDR2/LPDDR Combo PHY for Chip Application; UMC 55nm LP/RVT LowK Logic Process Analog_IP 55nm Bronze
FXDDR3D502HF0A Data Block of DDR3/DDR3L/DDR2/LPDDR2/LPDDR Combo PHY for Chip Application (compliant to DFI); UMC 55nm SP/RVT LowK Logic Process Analog_IP 55nm Contact Sales
 
FXDDR3D502HH0L Data Block of DDR3/DDR3L/DDR2/LPDDR2/LPDDR Combo PHY for Chip Application (compliant with DFI spec); UMC 40nm LP LowK Logic Process Analog_IP 40nm Silver Minus
FXDDR3DFC502HH0L DDR3 Combo PHY Data Block for solder bump application; UMC 40nm LP/RVT Logic Process Analog_IP 40nm Contact Sales
 
FXDDR3LTD102HH0L DDR3/DDR3L/LPDDR2 combo PHY ( not support DDR3 leveling function), data block;UMC 40nm LP/RVT LowK Logic Process . Analog_IP 40nm Contact Sales
 
 
Interface Solution > DDR
> DDR PHY - Data Block > DDR4 - Data Block 
Cell Name Descriptions Type Process Gradation Literature
FXDDR4D16FC101HH0L 40nm LP DDR3/4 LPDDR23 COMBO PHY DATA Block for Flip Chip usage Analog_IP 40nm Contact Sales
 
FXDDR4DFD612HH0L Data Block of DDR3/DDR4/LPDDR2/LPDDR3 Combo PHY for copper pillar bump Flip chip version ; UMC 40nm LP LowK Logic Process Analog_IP 40nm Contact Sales
 
Interface Solution > DDR
> DDR PHY - Data Block > DDR4 PHY - Data Block 
Cell Name Descriptions Type Process Gradation Literature
FXDDR4D16FC602HH0L Data Block of DDR3/DDR4/LPDDR2/LPDDR3 Combo PHY for Solder bump Flip chip version ; UMC 40nm LP LowK Logic Process Analog_IP 40nm Contact Sales
 
 
Interface Solution > DDR
> DDR PHY - Data Block > LPDDR2 - Data Block 
Cell Name Descriptions Type Process Gradation Literature
FXLPDDR2D102HH0L_SIP 40nm LPDDR2-PHY data block for SIP Analog_IP 40nm Contact Sales
 
 
Interface Solution > DDR
> DDR PHY - Data Block > LPDDR3 - Data Block 
Cell Name Descriptions Type Process Gradation Literature
FXDDR4DFD612EWHJ0C Data Block of DDR3/DDR4/LPDDR2/LPDDR3 Combo PHY for copper pillar bump Flip chip version ; UMC 28nm Logic and Mixed-Mode Low-K HPC Process Analog_IP 28nm Contact Sales
 
FXDDR4DFD612EWHJ0P Data Block of DDR3/DDR4/LPDDR2/LPDDR3 Combo PHY for copper pillar bump Flip chip version ; UMC 28nm Logic and Mixed-Mode Low-K HPC+ Process Analog_IP 28nm Contact Sales
 
FXDDR4DFD612NSHJ0C Data Block of DDR3/DDR4/LPDDR2/LPDDR3 Combo PHY for copper pillar bump Flip chip version ; UMC 28nm Logic and Mixed-Mode Low-K HPC Process Analog_IP 28nm Contact Sales
 
FXDDR4DFD612NSHJ0P Data Block of DDR3/DDR4/LPDDR2/LPDDR3 Combo PHY for copper pillar bump Flip chip version ; UMC 28nm Logic and Mixed-Mode Low-K HPC+ Process Analog_IP 28nm Contact Sales
 
FXDDR4DFD622NSHJ0P Data Block of DDR3/DDR4/LPDDR2/LPDDR3 Combo PHY for copper pillar bump Flip chip version ; UMC 28nm Logic and Mixed-Mode Low-K HPC+ Process Analog_IP 28nm Contact Sales
 
FXLPDDR3D16W101HH0L 40nm LPDDR3-PHY Data block for LightCo ; UMC 40nm LP/LVT Logic Process Analog_IP 40nm Contact Sales
 
 
Interface Solution > Ethernet
> Ethernet PHY 
Cell Name Descriptions Type Process Gradation Literature
FXEDP310NSHJ0L FXEDP310HJ0L, 10BASE-T/100BASE-TX/100BASE-FX Energy Efficient Ethernet PHY; UMC 28nm HLP process, voltage mode TX Analog_IP 28nm Contact Sales
 
FXEDP410EWHJ0P 10BASE-T/100BASE-TX/100BASE-FX/1000BASE-T Energy Efficient Ethernet PHY; UMC 28nm HPC+ process Analog_IP 28nm Contact Sales
 
 
Interface Solution > Ethernet
> Ethernet PHY > 10/100 TX Ethernet PHY 
Cell Name Descriptions Type Process Gradation Literature
FXEDP110HC0A 10/100 Base-TX Fast Ethernet PHY; UMC 0.13um Logic HS (FSG) process. Analog_IP 0.13um Gold
FXEDP110HD0A 10/100 Base-TX Fast Ethernet PHY; UMC 90nm SP/RVT Low-K Logic Process Analog_IP 90nm Silver
FXEDP110HE0A 10/100 Base-TX Fast Ethernet PHY; UMC 65nm SP/RVT Low-K Logic Process Analog_IP 65nm Silver Minus
FXEDP110HJ0C 10BASE-T/100BASE-TX/100BASE-FX Energy Efficient Ethernet PHY; UMC 28nm HPC/Low-K process Analog_IP 28nm Contact Sales
 
FXEDP112HA0A 10/100 Base-TX Fast Ethernet PHY; UMC 0.18um MMC process. Analog_IP 0.18um Platinum
FXEDP116HC0H 0.13um DSP Based Fast Ethernet PHY, based on FXEDP110HC0A HJ026a and add 100BASE-FX feature. Analog_IP 0.13um Bronze
FXEDP118HR0B 10/100 Base-TX/FX Energy Efficient Ethernet PHY; UMC 0.11um HS/AE (AL Advance Enhancement) Logic Process. Analog_IP 0.11um Silver Minus
FXEDP310EWHJ0L FXEDP310HJ0L, 10BASE-T/100BASE-TX/100BASE-FX Energy Efficient Ethernet PHY; UMC 28nm HLP process Analog_IP 28nm Contact Sales
 
FXEDP310HR0B Voltage mode 10/100 Base-TX/FX Energy Efficient Ethernet PHY; Support EtherCAT and cable diagnostic; UMC 0.11um HS/AE Logic Process. Analog_IP 0.11um Bronze
 
Interface Solution > Ethernet
> Ethernet PHY > 10/100/1000 TX Ethernet PHY 
Cell Name Descriptions Type Process Gradation Literature
FXEDP210HJ0C 10BASE-T/100BASE-TX/100BASE-FX/1000BASE-T Gigabit Energy Efficient Ethernet PHY; UMC 28nm HPC/Low-K process Analog_IP 28nm Contact Sales
FXEDP210HJ0P 10BASE-T/100BASE-TX/100BASE-FX/1000BASE-T Gigabit Energy Efficient Ethernet PHY; UMC 28nm HPC+/LOW_K process Analog_IP 28nm Contact Sales
 
FXEDP410HH0L 10BASE-T/100BASE-TX/100BASE-FX/1000BASE-T Gigabit Energy Efficient Ethernet PHY; UMC 40nm LP/RVT Low-K Logic Process Analog_IP 40nm Contact Sales
 
 
Interface Solution > LVDS
> FPD LVDS BIAS Circuit 
Cell Name Descriptions Type Process Gradation Literature
FXLVBGR030HH0L 10 lane FXSLVTX030HH0L bias circuit ; UMC 40nm LP/RVT Logic Process Analog_IP 40nm Silver
 
Interface Solution > LVDS
> FPD LVDS Receiver 
Cell Name Descriptions Type Process Gradation Literature
FXLVDS168HR0H Low power LVDS Receiver IO 50Mbps; UMC 0.11 um Logic HS/FSG (Cu) Process Analog_IP 0.11um Contact Sales
 
FXLVDSRX060HH0L LVDS RX,UMC 40nm LP/RVT LowK Logic Process Analog_IP 40nm Silver
FXLVDSRX080HH0L LVDS RX IO PAD 500 Mbps ,UMC 40nm LP/RVT LowK Logic Process Analog_IP 40nm Contact Sales
 
FXLVDSRX080HH0L_BUMP LVDS RX IO PAD 500 Mbps, UMC 40nm LP/RVT LowK Logic Process, Bump pad. Analog_IP 40nm Contact Sales
 
FXLVIORX800HH0L 1.8v LVDS RX IO 800Mbps, UMC 40nm LP/RVT LowK Logic Process Analog_IP 40nm Contact Sales
FXLVRX012HC0H DLL-based LVDS RX; VCC=3.3 for 20M~135MHz and VCC=2.5 for 20M~100MHz operation freq. 1data(581Mbps) +1clock(83Mhz). UMC 0.13um HS FSG Logic Process Analog_IP 0.13um Contact Sales
 
FXLVRX015HC0H DLL-based LVDS RX,VCC=3.3V for 11.5MHz ~ 34.6MHz operation frequency, UMC 0.13um HS FSG Logic Process Analog_IP 0.13um Contact Sales
 
FXLVRX020HA0A 0.18UM RX (PAD); UMC 0.18um GII Process Analog_IP 0.18um Silver
FXLVRX020HC0H 0.13um LVDS RX I/O PAD; UMC 0.13um HS HVT-FSG Process. Analog_IP 0.13um Silver
FXLVRX020HD0A 2.5V LVDS Receiver 8~135MHz; 90nm SP process Analog_IP 90nm Silver
FXLVRX020HH0L 3.3v LVDS RX,UMC 40nm LP/RVT LowK Logic Process Analog_IP 40nm Contact Sales
 
FXLVRX020HJ0C LVDS RX Receives serial LVDS signal and de-serialize them into parallel format ; UMC 28nm HPC Logic Process Analog_IP 28nm Contact Sales
FXLVRX020HJ0P UMC 28nm HPC+ Logic Process, LVDS RX Receives serial LVDS signal and de-serialize them into parallel format Analog_IP 28nm Contact Sales
 
FXLVRX020HR0B Low power LVDS Receiver 800Mbps; UMC 0.11um HS/AE (AL Advanced Enhancement) Logic Process Analog_IP 0.11um Contact Sales
 
FXLVRX023HF0A DLL-based LVDS RX 3.3v/1.0v ; 55nm SP/RVT LowK Logic Process Analog_IP 55nm Contact Sales
 
FXLVRX024HF0A 55nm-SP, FPD-Link Receiver, 3.3V/1.0V, 4 data plus 1 clock channel, 16~85MHz, DLL type, Analog_IP 55nm Contact Sales
FXLVRX025HF0A DLL-based LVDS RX 3.3v/1.0v ; 55nm SP/RVT LowK Logic Process Analog_IP 55nm Contact Sales
 
FXLVRX030HF0A Low power LVDS Receiver IO 500Mbps; UMC 55nm SP/RVT LowK Logic Process Analog_IP 55nm Silver
FXLVRX030HH0L 3.3v LVDS RX, 3 data lane and 1 clock lane using UMC 40nm LP/RVT LowK Logic Process Analog_IP 40nm Bronze
FXLVRX038HH0L 8 Lanes LVDS RX IO PAD, UMC 40nm LP/RVT LowK Logic Process Analog_IP 40nm Contact Sales
 
FXLVRX050HH0L 3.3v LVDS RX IO 1.25Gbps, UMC 40nm LP/RVT LowK Logic Process Analog_IP 40nm Contact Sales
 
FXLVRX060HC0H DLL-based LVDS RX; VCC=3.3 for 20M~135MHz and VCC=2.5 for 20M~100MHz operation freq.; UMC 0.13um HS FSG Logic Process Analog_IP 0.13um Silver
 
FXLVRX060HD0A Low power LVDS Receiver 700Mbps ; UMC 90nm SP/RVT Lowk Logic Process Analog_IP 90nm Silver
FXLVRX060HF0A DLL-based LVDS RX ; 55nm SP/RVT LowK Logic Process Analog_IP 55nm Silver
FXLVRX080HD0A LVDS RX IO ; UMC 90nm SP/RVT LowK Logic Process Analog_IP 90nm Silver Minus
FXLVRX080HF0F LVDS RX IO PAD 300 Mbps with combo GPIO , UMC 55nm eflash/RVT LowK Logic Process Analog_IP 55nm Silver
FXLVRX080HF0L LVDS RX IO PAD 500 Mbps ,UMC 55nm LP/RVT LowK Logic Process Analog_IP 55nm Silver
FXLVRX080HH0L LVDS RX IO PAD 500 Mbps, UMC 40nm LP/RVT LowK Logic Process, for flip chip Analog_IP 40nm Contact Sales
 
FXLVRX082HC0H 20M~135MHz DLL-based LVDS RX; UMC 0.13um HS/FSG Process Analog_IP 0.13um Silver
FXLVRX4312HF0A 4-Data Channel DLL-based LVDS RX ; 55nm SP/RVT LowK Logic Process ; 3.3V IO / 1.0V Core ; Clock Range 10Mhz~180Mhz Analog_IP 55nm Contact Sales
FXLVRX5308HH0L 5-Data Channel DLL-based LVDS RX ; 40LP/RVT low-K process ; 3.3V IO / 1.1V Core ; Clock Range 16Mhz~120Mhz Analog_IP 40nm Contact Sales
FXLVRXBS050HH0L The bias block only for FXLVRX050HH0L, UMC 40nm LP/RVT LowK Logic Process Analog_IP 40nm Contact Sales
 
FXLVRXBS080HF0F The bias block only for FXLVRX080HF0F, UMC 55nm eflash/RVT LowK Logic Process Analog_IP 55nm Contact Sales
 
FXLVRXBS080HF0L The bias block only for FXLVRX080HF0L, UMC 55nm LP/RVT LowK Logic Process Analog_IP 55nm Contact Sales
 
FXLVRXBS080HH0L The bias block only for FXLVDSRX080HH0L, UMC 40nm LP/RVT LowK Logic Process Analog_IP 40nm Contact Sales
 
 
Interface Solution > LVDS
> FPD LVDS Transmitter 
Cell Name Descriptions Type Process Gradation Literature
FXLVTX020HA0A 0.18um TX PAD; UMC 0.18um LOGIC RVT-FSG Process. Analog_IP 0.18um Silver
FXLVTX020HC0H 0.13um LVDS TX I/O PAD; UMC 0.13um HS HVT-FSG Process Analog_IP 0.13um Silver
FXLVTX020HF0A 2.5V LVDS Transmitter 16~178MHz; 55nm SP/RVT LowK Logic Process Analog_IP 55nm Silver
FXLVTX020HH0L 2.5V FPD-link LVDS Transmitter 16~178.6MHz; UMC 40nm LP Low-K process Analog_IP 40nm Bronze
FXLVTX020HJ0C 3.3V FPD-link LVDS Transmitter 16~100MHz; UMC 28nm HPC process Analog_IP 28nm Contact Sales
FXLVTX020HJ0P 3.3V FPD-link LVDS Transmitter 16~100MHz; UMC 28nm HPC plus proces Analog_IP 28nm Contact Sales
 
FXLVTX020HR0B 0.11um LVDS TX I/O PAD ; UMC 0.11um HS/AE (AL Advanced Enhancement) Logic Process Analog_IP 0.11um Silver Minus
FXLVTX030HD0A Single port LVDS Transmitter PAD 1.25Gbps; UMC 90nm SP/RVT low-K process Analog_IP 90nm Gold
FXLVTX030HF0A 2.5V LVDS Transmitter 700Mbps; UMC 55nm SP LowK Logic Process Analog_IP 55nm Silver
FXLVTX030HH0L 2.5V LVDS Transmitter 700Mbps; UMC 40nm LP LowK Logic Process Analog_IP 40nm Bronze
FXLVTX030HH0L_BUMP 2.5V LVDS Transmitter 700Mbps; UMC 40nm LP LowK Logic Process. (Modify layout ) Analog_IP 40nm Contact Sales
 
FXLVTX030HJ0C LVDS Transmitter 700Mbps; UMC 28nm HPC Process Analog_IP 28nm Contact Sales
 
FXLVTX033HD0A 3.3V LVDS Transmitter 700Mbps; 90nm SP/RVT low-L process Analog_IP 90nm Silver Minus
FXLVTX033HF0A 3.3V LVDS Transmitter 700Mbps;UMC 55nm SP/RVT LowK PROCESS Analog_IP 55nm Silver
FXLVTX040HH0L 3.3V LVDS Transmitter 700Mbps; UMC 40nm LP LowK Logic Process Analog_IP 40nm Bronze
FXLVTX050HH0L 2.5V LVDS Transmitter 1.25Gbps; UMC 40nm LP LowK Logic Process. Analog_IP 40nm Bronze
FXLVTX081HA0A 1.8V/3.3V 85MHz 35:5 LVDS Transmitter; UMC 0.18um GII logic process. Analog_IP 0.18um Silver
 
FXLVTX100HF0A 100MHz Reference Clock Single-end to Differential Buffer for PCIE Gen.II; UMC 55nm SP/RVT LowK Logic Process Analog_IP 55nm Silver Minus
FXLVTX100HH0L 100MHz single-ended to differential clock buffer for UMC 40nm LP. Analog_IP 40nm Bronze
FXLVTX169HC0H 100MHz Reference Clock Single-end to Differential Buffer for PCIE Gen.I; UMC 0.13um HS/FSG LOGIC/MIXEDMODE Enhance Process Analog_IP 0.13um Bronze
FXLVTX320HF0A 3.3V LVDS Transmitter 16~100MHz; 55nm SP/RVT LowK Logic Process Analog_IP 55nm Silver
FXLVTX324HD0A 3.3V 4 channel LVDS Transmitter 8~100MHz; UMC 90nm SP/RVT LowK Process Analog_IP 90nm Bronze
 
Interface Solution > LVDS
> IO LVDS Receiver 
Cell Name Descriptions Type Process Gradation Literature
FXLVIORX1105EWHJ0C 28nm HPC, LVDS RXIO, 500Mbps, 1.8V/0.9V Analog_IP 28nm Contact Sales
FXLVIORX1105NSHJ0C 28nm HPC, LVDS RXIO, 500Mbps, 1.8V/0.9V Analog_IP 28nm Contact Sales
 
FXLVIORX1110HH0L LVDS RX IO PAD 1000 Mbps, UMC 40nm LP/RVT LowK Logic Process. Analog_IP 40nm Contact Sales
FXLVIORX1309HR0B LVDS RXIO 945Mbps, 3.3V/1.2V, UMC 0.11um HS/AE(AL Advanced Enhancement) Logic Process Analog_IP 0.11um Contact Sales
 
Interface Solution > LVDS
> IO LVDS Transmitter 
Cell Name Descriptions Type Process Gradation Literature
FXLVIOTX1307HH0L LVDS Combo-IO TX 750Mbps; UMC 40LP LowK Process; 3.3V IO / 1.1V Core; Include BGA Analog_IP 40nm Contact Sales
FXLVIOTX1309HR0B LVDS TXIO 945Mbps, 3.3V/1.2V, UMC 0.11um HS/AE (AL Advanced Enhancement) Logic Process Analog_IP 0.11um Contact Sales
 
Interface Solution > LVDS
> Sub-LVDS Receiver 
Cell Name Descriptions Type Process Gradation Literature
FXSLVRX112HJ0C 1.8V Sub-LVDS Receiver 650Mbps; UMC 28nm HPC process Analog_IP 28nm Contact Sales
 
 
Interface Solution > LVDS
> Sub-LVDS Transmitter 
Cell Name Descriptions Type Process Gradation Literature
FXSLVTX030HH0L 1.8V Sub-LVDS Transmitter 1200Mbps; UMC 40nm LP/RVT Logic Process Analog_IP 40nm Silver
 
Interface Solution > MIPI
 
Cell Name Descriptions Type Process Gradation Literature
FXDPHYTX8111HJ0C MIPI Transmitter 80Mbps~1.5Gbps without LP-mode ; UMC 28nm HPC Logic and Mixed-Mode Process Analog_IP 28nm Contact Sales
 
 
Interface Solution > MIPI
> MIPI CPHY > MIPI CPHY Receiver 
Cell Name Descriptions Type Process Gradation Literature
FXCDPHYRX3401HJ0C MIPI Receiver CPHY 80Msps~2.5Gsps; DPHY 80Mbps~2.5Gbps ; UMC 28nm HPC process Analog_IP 28nm Contact Sales
 
 
Interface Solution > MIPI
> MIPI CPHY > MIPI CPHY Transmitter 
Cell Name Descriptions Type Process Gradation Literature
FXCDPHYTX3401HJ0C MIPI Transmitter CPHY 80Msps~2.5Gsps; DPHY 80Mbps~2.5Gbps ; UMC 28nm HPC process Analog_IP 28nm Contact Sales
 
 
Interface Solution > MIPI
> MIPI DPHY > MIPI DPHY Receiver 
Cell Name Descriptions Type Process Gradation Literature
FXDPHYRX12112HJ0C MIPI DPHY Reciever 80Mbps~2.5Gbps ; UMC 28nm HPC Logic Process Analog_IP 28nm Contact Sales
 
FXDPHYRX12112HJ0P MIPI DPHY Reciever 80Mbps~2.5Gbps ; UMC 28nm HPC+ Process Analog_IP 28nm Contact Sales
 
FXDPHYRX4111HJ0C MIPI Receiver, DPHY V1.1 RX ; UMC 28nm HPC process Analog_IP 28nm Contact Sales
 
FXDPHYRX4112HJ0C MIPI Receiver, DPHY V1.2 RX ; UMC 28nm HPC process Analog_IP 28nm Bronze
FXDPHYRX4112HJ0P MIPI RX 80Mbps~2.5Gbps ; UMC 28nm HPC+ process Analog_IP 28nm Contact Sales
 
FXDPHYRX4112NSHJ0P MIPI RX 80Mbps~2.5Gbps ; UMC 28nm HPC+ process Analog_IP 28nm Contact Sales
FXDPHYRX420HH0L MIPI Receiver 80Mbps-1.5Gbps; 40nm LP LowK Logic Process Analog_IP 40nm Silver
FXDPHYRX420HH0L_GPIO MIPI Receiver 80Mbps-1Gbps; 40nm LP LowK Logic Process Analog_IP 40nm Silver
FXDPHYRX4212HJ0C MIPI CSI Receiver 1G/ SLVDS 1G /HiSPi 1G, 1.8V/3.3V GPI 100MHz; UMC 28nm HPC Logic Process Analog_IP 28nm Contact Sales
 
FXDPHYRX8112HJ0C MIPI Receiver,DPHY RX V1.2; UMC 28nm HPC Logic and Mixed-Mode Process Analog_IP 28nm Contact Sales
 
FXDPHYTX4112NSHJ0P MIPI Transmitter 80Mbps~2.5Gbps; UMC 28nm HPC+ process Analog_IP 28nm Contact Sales
 
FXMPRX010HF0A MIPI Receiver 80Mbps ~ 1.5Gbps; UMC 55nm SP/RVT LowK Logic Process Analog_IP 55nm Silver Minus
FXMPRX010HH0L MIPI Receiver 80Mbps-1.5Gbps; 40nm LP LowK Logic Process Analog_IP 40nm Silver Minus
FXMPRX020HH0L MIPI Receiver 80Mbps-1Gbps; Combo PHY for MIPI & HiSPi & LVDS & SubLVDS,40nm LP LowK Logic Process Analog_IP 40nm Silver Minus
FXMPRX030HH0L MIPI Receiver 80Mbps-1Gbps; Combo PHY for MIPI & HiSPi & LVDS & SubLVDS,40nm LP LowK Logic Process, Two Lane. Analog_IP 40nm Silver Minus
 
Interface Solution > MIPI
> MIPI DPHY > MIPI DPHY Transmitter 
Cell Name Descriptions Type Process Gradation Literature
FXDPHYTX1111HJ0C MIPI Transmitter 80Mbps~1.5Gbps ; UMC 28nm HPC Logic Process Analog_IP 28nm Contact Sales
 
FXDPHYTX1112HJ0C MIPI Transmitter 80Mbps~2.5Gbps ; UMC 28nm HPC Logic Process Analog_IP 28nm Contact Sales
 
FXDPHYTX210HH0L MIPI Transmitter 80Mbps~1.5Gbps with 1-clock lane, 2-data lanes; UMC 40nm LP/RVT/LVT Low-K process Analog_IP 40nm Contact Sales
 
FXDPHYTX4111HJ0C MIPI Transmitter 80Mbps~1.5Gbps ; UMC 28nm HPC Logic Process Analog_IP 28nm Contact Sales
 
FXDPHYTX4112HJ0C MIPI Transmitter 80Mbps~2.5Gbps ; UMC 28nm HPC Logic and Mixed-Mode Process Analog_IP 28nm Bronze
 
FXDPHYTX4112HJ0P MIPI Transmitter 80Mbps~2.5Gbps ; UMC 28nm HPC+ process Analog_IP 28nm Contact Sales
 
FXDPHYTX411HH0L MIPI Transmitter 80Mbps~1.5Gbps; UMC 40nm LP/RVT/LVT Low-K process Analog_IP 40nm Contact Sales
 
FXDPHYTX4212NSHJ0C MIPI Transmitter 80Mbps~2.5Gbps cost down ; UMC 28nm HPC process Analog_IP 28nm Contact Sales
 
FXDPHYTX430HH0L MIPI Transmitter 80Mbps~1500Mbps combo with CMOS input; UMC 40nm LP Low-K process Analog_IP 40nm Silver
FXDPHYTX8112HJ0C MIPI Transmitter 80Mbps~2.5Gbps ; UMC 28nm HPC Logic Process Analog_IP 28nm Contact Sales
 
FXMPTX010HF0A MIPI Transmitter 80Mbps~1.5Gbps; UMC 55nm SP/RVT LowK Logic Process Analog_IP 55nm Silver Minus
FXMPTX010HH0L MIPI Transmitter 80Mbps~1500Mbps; UMC 40nm LP/RVT Low-K process Analog_IP 40nm Silver Minus
 
Interface Solution > MIPI
> MPHY > MIPI MPHY PMA 
Cell Name Descriptions Type Process Gradation Literature
FXMPHY010HH0L MIPI MPHY 6Gbps/lane; UMC 40nm LP Low-K process. Analog_IP 40nm Contact Sales
 
 
Interface Solution > MIPI
> On Die Termination for MIPI 
Cell Name Descriptions Type Process Gradation Literature
FXODT010NSHJ0C MIPI On-Die Termination ; UMC 28nm HPC process Analog_IP 28nm Contact Sales
 
 
Interface Solution > ONFI4.0
> ONFI PHY 
Cell Name Descriptions Type Process Gradation Literature
FXONFI4COMP100HH0L ONFI PHY Compensation Block for ONFI4.0 application; UMC 40nm LP/RVT Logic Process Analog_IP 40nm Contact Sales
 
 
Interface Solution > PCI Express
> PCIe Controller > PCIe-GEN4 Controller 
Cell Name Descriptions Type Process Gradation Literature
FTPCIE440 PCIe Gen4 x8 Lane Endpoint Controller Soft_IP Contact Sales
 
FTPCIE4PCS PCIe Gen4 PCS Soft IP Soft_IP Contact Sales
 
 
Interface Solution > PCI Express
> PCIe PHY > PCIe-GEN PHY 
Cell Name Descriptions Type Process Gradation Literature
FXPCIE100HA0A PCI-Express PHY with PIPE interface, 1 lane PCI-E PHY; UMC 0.18um Logic GII (RVT) process Analog_IP 0.18um Silver
FXPCIE166HA0A PCI-Express PHY with PIPE interface, 1 lane PCI-E PHY; UMC 0.18um Logic GII (RVT) process Analog_IP 0.18um Silver
 
FXPCIE169HC0H PCI-Express PHY with PIPE interface, 1 lane PCI-E PHY with low power feature; UMC 0.13um HS/FSG Logic Process Analog_IP 0.13um Silver
 
Interface Solution > PCI Express
> PCIe PHY > PCIe-GEN2 PHY 
Cell Name Descriptions Type Process Gradation Literature
FXPCIE200HD0A PCI-Express II PHY; UMC 90nm SP/RVT Low-K Process Analog_IP 90nm Silver
FXPCIE268HE0L PCIE Gen.II PHY; UMC 65nm LP/RVT LowK Logic Process. Analog_IP 65nm Contact Sales
 
FXPCIE268HF0A PCIE Gen.II ; UMC 55nm SP/RVT LowK Logic Process Analog_IP 55nm Silver
FXPCIE4X200HD0A 4x lane PCI Express Gen II PHY; UMC 90nm SP/RVT Low-K Logic Process Analog_IP 90nm Silver Minus
 
Interface Solution > Serdes
> 1.25G to 16G Serdes 
Cell Name Descriptions Type Process Gradation Literature
FXSERDES4160NSHJ0P 28nm HPC+ 16G Serdes Analog_IP 28nm Contact Sales
 
 
Interface Solution > Serdes
> 1.25G to 16G Serdes > Chassis Management Module for 1.25G to 16G Serdes 
Cell Name Descriptions Type Process Gradation Literature
FXCMM0012NSHJ0C Programmable SERDES, CMM part 1~12.5G Data Rate, UMC 28mm HPC process Analog_IP 28nm Contact Sales
 
 
Interface Solution > Serdes
> 1.25G to 16G Serdes > TX+RX Lane Operating for 1.25G to 16G Serdes 
Cell Name Descriptions Type Process Gradation Literature
FXTXRX0012NSHJ0P Programmable SERDES, TXRX part 1~12.5G Data Rate, UMC 28mm HPC+ process Analog_IP 28nm Contact Sales
 
 
Interface Solution > Serdes
> 1.25G to 8G Serdes > Chassis Management Module for 1.25G to 8G Serdes 
Cell Name Descriptions Type Process Gradation Literature
FXCMM0010HJ0C CMM lane operating from 1.25G~8G ,UMC 28nm HPC Process Analog_IP 28nm Contact Sales
 
 
Interface Solution > Serdes
> 1.25G to 8G Serdes > TX+RX Lane Operating for 1.25G to 8G Serdes 
Cell Name Descriptions Type Process Gradation Literature
FXTXRX0010HJ0C Analog part of TX+RX lane operating at 1.25G~8Gbps , UMC 28nm HPC Process Analog_IP 28nm Contact Sales
 
 
Interface Solution > Serdes
> 1G to 12.5G Serdes > Chassis Management Module for 1G to 12.5G Serdes 
Cell Name Descriptions Type Process Gradation Literature
FXCMM0012NSHJ0P Programmable SERDES, CMM part 1~12.5G Data Rate, UMC 28mm HPC+ process Analog_IP 28nm Contact Sales
 
 
Interface Solution > Serdes
> 4-Lane 10G Serdes 
Cell Name Descriptions Type Process Gradation Literature
FXSERDES0410HJ0C 28nm HPC x4 lane 10 Gbps SERDES Analog_IP 28nm Contact Sales
 
 
Interface Solution > Serdes
> 4-Lane 12.5G Serdes 
Cell Name Descriptions Type Process Gradation Literature
FXSERDES0412HJ0P UMC 28nm HPC+, 4-Lane 1.25~12.5 Gbps SERDES Analog_IP 28nm Contact Sales
 
FXSERDES0412NSHJ0P UMC 28nm HPC+, 4-Lane 1.25~12.5 Gbps SERDES Analog_IP 28nm Contact Sales
 
FXSERDES0416HJ0C UMC 28nm HPC/Low-K process , 1.25G-12.5Gbps 4-Lane SERDES Analog_IP 28nm Contact Sales
 
Interface Solution > Serdes
> 4-Lane 28G Serdes 
Cell Name Descriptions Type Process Gradation Literature
FXSERDES4280HJ0C 28Gb/s 4 lane high-speed SerDes; UMC 28nm HPC Logic Std/HS process Analog_IP 28nm Contact Sales
 
 
Interface Solution > Serial ATA
> 1.5G to 3G SATA > 1.5G to 3G SATA PMA 
Cell Name Descriptions Type Process Gradation Literature
FXESATA303HA0A 1.5G/3.0Gbps 1 port Serial ATA PHY and ESATA ; UMC 0.18um Logic GII process. Analog_IP 0.18um Silver
 
Interface Solution > Serial ATA
> 3G/1.5G SATA 
Cell Name Descriptions Type Process Gradation Literature
FXSATA168HC0H 3G/1.5G Serial ATA PHY; UMC 0.13um HS/FSG Logic Process Analog_IP 0.13um Gold
FXSATA168HD0A Serial ATA I II PHY;UMC 90nm SP/RVT Lowk Logic Process Analog_IP 90nm Silver
FXSATA168HR0B 3G/1.5G Serial ATA PHY; UMC 0.11um HS/AE (AL Advance Enhancement) Logic Process Analog_IP 0.11um Silver
FXSATA168HR0H 3G/1.5G Serial ATA PHY; UMC 0.11um HS/FSG Logic Process Analog_IP 0.11um Gold
FXSATA1X300HC0H Serial ATA (SATA) physical layer that provides a complete range of host and device functions; UMC 0.13um Logic HS(FSG) process Analog_IP 0.13um Silver
FXSATA1X310HC0U Over sampling 1 port 3G/1.5G SATA PHY ; UMC 0.13um HS+LL/FSG Logic Process Analog_IP 0.13um Silver
FXSATA268HF0A Serial ATA I,II PHY ;UMC 55nm SP/RVT LowK Logic Process Analog_IP 55nm Contact Sales
 
 
Interface Solution > Serial ATA
> SATA Controller 
Cell Name Descriptions Type Process Gradation Literature
FTSATA3237 SATA 3.0 PCS. Soft_IP Contact Sales
 
 
Interface Solution > Serial ATA
> SATA I,II,III 
Cell Name Descriptions Type Process Gradation Literature
FXSATA368HF0A Serial ATA I,II,III PHY ; UMC 55nm SP/RVT LowK Logic Process Analog_IP 55nm Silver
FXSATA368HR0H 6G/3G/1.5G Serial ATA PHY; UMC 0.11um HS/FSG Logic Process Analog_IP 0.11um Silver
 
Interface Solution > USB/OTG
> USB PHY > USB 1.1 OTG PHY 
Cell Name Descriptions Type Process Gradation Literature
FZOTG100HC0G USB 1.1 On-The-Go transceiver; UMC 0.13um Logic SP (FSG) process. Analog_IP 0.13um Silver
FZOTG100HD0A USB 1.1 OTG PHY; UMC 90nm SP/RVT low-K logic process Analog_IP 90nm Silver
FZOTG100HD0K USB1.1 PHY Feature USB 1.1 Type PHY; Technology Type process USB 1.1 On-The-Go PHY; UMC 90nm Logic LL process Analog_IP 90nm Silver Minus
FZOTG100HE0C USB 1.1 On-The-Go PHY; UMC 65nm SP/HVT Logic Low-K Process Analog_IP 65nm Silver Minus
FZOTG100HE0K USB 1.1 OTG PHY; UMC 65nm logic LL/RVT (Low K) process Analog_IP 65nm Silver
FZOTG100HR0B USB1.1 PHY Feature USB 1.1 On-The-Go PHY; UMC 0.11um HS/AE (AL Advanced Enhancement) Logic Process, without internal power clamping circuit Analog_IP 0.11um Silver
FZOTG110H90A USB 1.1 On-The-Go transceiver (ECN spec); UMC 0.25um Logic process. Analog_IP 0.25um Silver
FZOTG110HA0A USB 1.1 On-The-Go transceiver (ECN spec); UMC 0.18um Logic GII process. Analog_IP 0.18um Silver
FZOTG110HA0F USB 1.1 OTG; UMC 0.18um e-flash process Analog_IP 0.18um Silver
FZOTG110HB0G USB 1.1 On-The-Go transceiver; UMC 0.15um SP Logic process. Analog_IP 0.15um Silver
FZOTG111HC0H 0.13um OTG PHY ; UMC 0.13um HS (FSG) process Analog_IP 0.13um Gold
FZOTG111HF0F USB1.1 PHY Feature USB 1.1 On-The-Go PHY; UMC 55nm Logic e-Flash Process Analog_IP 55nm Bronze
 
FZOTG111HF0G USB1.1 PHY Feature USB 1.1 On-The-Go PHY; UMC 55nm Logic Eflash Ultra Low Power Process Analog_IP 55nm Contact Sales
 
FZOTG111HF0L USB1.1 PHY Feature USB 1.1 On-The-Go PHY; UMC 55nm Logic Low Power Low-K Process Analog_IP 55nm Contact Sales
FZOTG111HR0B USB1.1 PHY Feature USB 1.1 On-The-Go PHY; UMC 0.11um HS/AE (AL Advanced Enhancement) Logic Process Analog_IP 0.11um Silver
 
FZOTG111HR0H USB1.1 PHY Feature USB 1.1 Type PHY; Technology Type process USB 1.1 On-The-Go PHY; UMC 0.11um HS/Copper Logic Process Analog_IP 0.11um Silver
 
Interface Solution > USB/OTG
> USB PHY > USB 1.1 PHY 
Cell Name Descriptions Type Process Gradation Literature
FZUSB100H70A USB 1.1 PHY ; UMC 0.5um Logic process 3.3V 1P3M Analog_IP 0.5um Silver
FZUSB100HA0A USB 1.1 PHY; UMC 0.18um GII process 1.8/3.3V 1P6M Analog_IP 0.18um Gold
FZUSB100HA0F USB 1.1 PHY; UMC 0.18um e-flash process Analog_IP 0.18um Silver
FZUSB100HC0H USB 1.1 PHY; UMC 0.13um Logic HS (FSG) process. Analog_IP 0.13um Silver
FZUSB110HB0G USB 1.1 PHY; UMC 0.15um SP Logic process. Analog_IP 0.15um Silver
FZUSB199HF0F USB 1.1 transceiver support crystal-less mode in USB system ; UMC 55nm eFlash Process Analog_IP 55nm Silver Minus
USBA0A1H USB 1.1 transceiver; UMC 0.18um Logic GII process. Analog_IP 0.18um Platinum
USBC0L1H USB 1.1 transceiver; UMC 0.13um Logic LL (FSG) process. Analog_IP 0.13um Silver
 
Interface Solution > USB/OTG
> USB PHY > USB 1.1 PHY - ID Detector 
Cell Name Descriptions Type Process Gradation Literature
FZUSBID100HE0C ID Detector for USB OTG Function ; UMC 65nm SP/HVT Low-K Logic Process Analog_IP 65nm Bronze
 
 
Interface Solution > USB/OTG
> USB PHY > USB 2.0 OTG PHY 
Cell Name Descriptions Type Process Gradation Literature
FZOTG230H90A USB 2.0 host On-The-Go PHY; UMC 0.25um Logic process. Analog_IP 0.25um Gold
FZOTG230HA0A USB 2.0 On-The-Go PHY; UMC 0.18um Logic GII RVT/FSG process. Analog_IP 0.18um Platinum
FZOTG230HA0F USB2.0 OTG PHY; UMC 0.18um E-flash process Analog_IP 0.18um Silver Minus
FZOTG230HC0H USB 2.0 On-The-Go PHY; UMC 0.13um Logic HS (FSG) process. Analog_IP 0.13um Silver
FZOTG2661HJ0C USB 2.0 On-The-Go PHY, analog part ; UMC 28nm HPC RVT Logic Process Analog_IP 28nm Contact Sales
 
FZOTG266HA0F USB2.0 OTG PHY ; UMC 0.18um eFlash Process Analog_IP 0.18um Silver Minus
FZOTG266HC0H USB 2.0 On-The-Go PHY; UMC 0.13um Logic HS (FSG) process Analog_IP 0.13um Gold
FZOTG266HC0L USB 2.0 On-The-Go PHY; UMC 0.13um LL process Analog_IP 0.13um Silver
FZOTG266HD0A USB2.0 OTG PHY; UMC 90nm SP RVT/LowK Process Analog_IP 90nm Silver
FZOTG266HD0K USB2.0 OTG PHY; UMC 90nm LL Lowk-RVT process 2.5V OD 3.3V Analog_IP 90nm Silver Minus
FZOTG266HE0C USB2.0 OTG (VDT and ID are included in PHY); UMC 65nm SP/HVT LowK Process Analog_IP 65nm Silver Minus
FZOTG266HE0K USB2.0 OTG PHY (VDT and ID are included in PHY) ; UMC 65nm Low Leakage RVT LowK Process Analog_IP 65nm Silver Minus
FZOTG266HE0L USB2.0 OTG PHY (VDT and ID are included in PHY) ; UMC 65nm LP/RVT LowK Logic Process Analog_IP 65nm Silver Minus
FZOTG266HF0A OTG USB 2.0 PHY (VDT and ID are included in PHY) ; UMC 55nm SP LowK Logic Process Analog_IP 55nm Silver
FZOTG266HF0F USB2.0 OTG PHY ; UMC 55nm eFlash Process Analog_IP 55nm Silver Minus
FZOTG266HF0L USB2.0 OTG PHY (VDT and ID are included in PHY) ; UMC 55nm LP LowK Logic Process Analog_IP 55nm Silver Minus
FZOTG266HH0L OTG USB2.0 UMC 40 nm LP/RVT process Analog_IP 40nm Silver
FZOTG266HH0L_LF USB2.0 OTG PHY UMC 40nm LP/RVT process, for Flip chip Bump type_LF Analog_IP 40nm Contact Sales
 
FZOTG266HJ0C USB 2.0 On-The-Go PHY; UMC 28nm HPC RVT Logic Process Analog_IP 28nm Silver Minus
FZOTG266HJ0P USB 2.0 On-The-Go PHY; UMC 28nm HPC+ RVT Logic Process Analog_IP 28nm Contact Sales
 
FZOTG266HL0A USB OTG 2.0 PHY ; UMC 0.153um Logic Process Analog_IP 0.153um Silver Minus
FZOTG266HR0B USB 2.0 OTG PHY ; UMC 0.11um HS/AE (AL Advance Enhancement) Logic Process Analog_IP 0.11um Silver
FZOTG266HR0D USB 2.0 OTG PHY ; UMC 0.11um HS AL Logic Process Analog_IP 0.11um (0.13um Shrink) Silver Minus
FZOTG266HR0H USB 2.0 On-The-Go PHY ; UMC 0.11um HS (FSG) Logic process Analog_IP 0.11um Silver Minus
FZOTG266HR0P UMC 0.11um eFlash Process ; USB 2.0 OTG PHY Analog_IP 0.11um Silver Minus
FZOTG268HH0L USB 2.0 On-The-Go PHY; UMC 40nm Logic LP/RVT Low-K Process Analog_IP 40nm Bronze
FZOTG268HJ0C USB2.0 On-The-Go PHY; UMC 28nm HPC RVT Logic Process cost down from FZOTG266HJ0C_A Analog_IP 28nm Contact Sales
FZOTG268HJ0L USB 2.0 On-The-Go PHY; UMC 28nm HLP Process Analog_IP 28nm Contact Sales
FZOTG268NSHJ0P USB 2.0 On-The-Go PHY; UMC 28nm HPC+ Analog_IP 28nm Contact Sales
 
Interface Solution > USB/OTG
> USB PHY > USB 2.0 OTG Two-Port PHY 
Cell Name Descriptions Type Process Gradation Literature
FZOTGTP201HH0L Two Port OTG USB2.0 PHY;BOAC version; Wire bonding;UMC 40 nm LP/RVT process. Analog_IP 40nm Silver Minus
 
Interface Solution > USB/OTG
> USB PHY > USB 2.0 PHY 
Cell Name Descriptions Type Process Gradation Literature
FZUSB236HA0A USB2.0 Analog PHY; UMC 0.18um Logic GII RVT/FSG process. Analog_IP 0.18um Platinum
FZUSB237HA0A USB2.0 PHY (Pin compatible to FZUSB236HA0A) ; UMC 0.18um GII Logic Process Analog_IP 0.18um Silver
FZUSB238HA0A USB2.0 PHY (Pure device mode); UMC 0.18um Logic GII RVT/FSG process Analog_IP 0.18um Gold
FZUSB238HA0I USB2.0 PHY; UMC 0.18um CIS process Analog_IP 0.18um Silver
FZUSB238HC0I USB 2.0 PHY ; UMC 0.13um CIS Process Analog_IP 0.13um Silver Minus
FZUSB238HC0L USB 2.0 PHY; UMC 0.13um Logic LL process Analog_IP 0.13um Platinum
FZUSB238HR0B USB 2.0 PHY; 0.11um HS/ALE standard logic process Analog_IP 0.11um Silver Minus
FZUSB238HR0H USB 2.0 PHY cost down version;UMC 0.11um HS Logic Process Analog_IP 0.11um Silver
FZUSB238HR0L USB 2.0 PHY cost down version;UMC 0.11um Logic LL process Analog_IP 0.11um Bronze
FZUSB299HH0L USB 2.0 PHY,crystal-less option; UMC 40nm LP/RVT process. Analog_IP 40nm Silver Minus
FZUSB299HR0B Crystal-Less USB2.0 PHY ; 0.11um HS/AE (AL Advanced Enhancement) Logic Process Analog_IP 0.11um Silver
 
Interface Solution > USB/OTG
> USB PHY > USB 2.0 Two-Port PHY 
Cell Name Descriptions Type Process Gradation Literature
FZUSBTP100HC0H USB 2.0 two port PHY; UMC 0.13um Logic HS(FSG) process Analog_IP 0.13um Gold
 
Interface Solution > USB/OTG
> USB PHY > USB 3.0 Crystal-less PHY 
Cell Name Descriptions Type Process Gradation Literature
FZUSB399HH0L Crystal-less USB 3.0 PHY ; UMC 40nm Logic/Mixed-Mode Low Power/RVT+LVT Process Analog_IP 40nm Silver Minus
 
Interface Solution > USB/OTG
> USB PHY > USB 3.0 OTG PHY 
Cell Name Descriptions Type Process Gradation Literature
FZOTG300HC0H USB3.0 OTG PHY ; UMC 0.13um HS/FSG Logic Process Analog_IP 0.13um Silver
FZOTG300HD0A USB 3.0 Transceiver ; UMC 90nm SP/RVT LowK Logic Process Analog_IP 90nm Silver Minus
FZOTG300HF0A USB3.0 PHY ; UMC 55nm SP/RVT LowK Logic Process Analog_IP 55nm Silver
FZOTG300HH0L USB 3.0 PHY ; UMC 40nm Logic/Mixed-Mode Low Power/RVT+LVT Process Analog_IP 40nm Silver
FZOTG300HJ0C USB 3.0 PHY ; UMC 28nm HPC RVT+LVT Logic Process Analog_IP 28nm Bronze
FZOTG300HJ0P USB 3.0 PHY; UMC 28nm HPC_Plus +RVT+LVT Logic Process Analog_IP 28nm Contact Sales
 
FZOTG300HR0B USB3.0 PHY ; UMC 0.11um HS/ALE Logic Process Analog_IP 0.11um Silver
FZOTG300HR0H USB3.0 PHY ; UMC 0.11um HS/FSG (Cu) Logic Process Analog_IP 0.11um Silver
FZOTG306HH0L USB 3.0 PHY ; UMC 40nm Logic/Mixed-Mode Low Power/RVT+LVT Process (Cost-down verison) Analog_IP 40nm Contact Sales
 
FZOTGC300HH0L USB 3.1 Gen.1 TYPE-C PHY ; UMC 40nm Logic/Mixed-Mode Low Power/RVT+LVT Process Analog_IP 40nm Contact Sales
 
Interface Solution > USB/OTG
> USB PHY > USB 3.1 PHY 
Cell Name Descriptions Type Process Gradation Literature
FZOTG306HJ0C Cost Down USB 3.1 Gen.1 PHY ; UMC 28nm HPC Logic Process Analog_IP 28nm Contact Sales
 
FZOTG306NSHJ0P USB 3.1 Gen1 PHY Costdown version ; UMC 28nm HPC+, SVT&LVT Logic Process A+D Part Naming with IO at North-South (NS) Analog_IP 28nm Contact Sales
FZOTG310HJ0C 28nm HPC USB3.1 gen2 PHY(10Gbps) Analog_IP 28nm Contact Sales
 
FZOTG310HJ0P 28nm HPC+ USB3.1 gen2 PHY(10Gbps) Analog_IP 28nm Contact Sales
 
 
Interface Solution > V-by-One
> VBO Receiver 
Cell Name Descriptions Type Process Gradation Literature
FXVBORX008HJ0C 600M to 4Gbps 4-lane V-By-One receiver, VCC=0.9V; UMC 28nm HPC LowK Logic Process. Analog_IP 28nm Contact Sales
FXVBORX008HJ0P Analog part of 600Mbps to 4Gbps 4-lane V-By-One receiver with embedded CDR circuit, VCC=0.9V; UMC 28nm HPC+ LowK Logic Process. Analog_IP 28nm Contact Sales
 
FXVBORX008NSHJ0C 28HPC VBO RX, 600Mbps~4Gbps, 4 lanes, bump version Analog_IP 28nm Contact Sales
 
 
Interface Solution > V-by-One
> VBO Transmitter 
Cell Name Descriptions Type Process Gradation Literature
FXVBOTX008HJ0P Analog part of 600Mbps to 4Gbps 8-lane V-By-One transmitter with embedded PLL circuit, VCC=0.9V; UMC 28nm HPC+ LowK Logic Process. Analog_IP 28nm Contact Sales