1-Port SRAM

Updated On:2018-07-17
Gradation
Faraday IPs are rated according to the IPs’ maturity and customer acceptance. They are graded by the rules described as below,


Platinum P Five (5) productions verified
Gold G Mass production proven
Silver S Silicon proven, Formal release
Silver Minus S- Manufacturing onging
Bronze B Pre-Silicon release
 
Memory Compiler > 1-Port SRAM
> 6TSRAM > High Density 1PSRAM, 6TSRAM, Peri HVT 
Cell Name Descriptions Type Process Gradation Literature
FSF0F_A_SHHVT 55nm eFlash with Peri HVT SP-SRAM compiler Memory_IP 55nm Silver
FSF0F_A_SHHVTRED UMC 55nm eFlash with Peri HVT & RED SP-SRAM Memory_IP 55nm Silver
FSF0F_A_SHRED UMC 55nm EFLASH Processy Single-Port SRAM with row repair Memory complier Memory_IP 55nm Bronze
FSF0G_A_SHHVT UMC 55nm eflash/ulp process standard synchronous high density single port SRAM memory compiler. Memory_IP 55nm Bronze
FSF0G_A_SHHVTRED UMC 55nm SST/ulp Logic process standard synchronous high density single port SRAM memory compiler. Memory_IP 55nm Bronze
FSF0G_W_SHHVT UMC 55nm embedded flash and embedded E2PROM ultra low power split-gate process synchronous well bias feature HVT periphery high density single port SRAM memory compiler. Memory_IP 55nm Bronze
FSF0G_W_SHHVTRED UMC 55nm embedded flash and embedded E2PROM ultra low power split-gate process synchronous well bias feature HVT periphery high density single port SRAM memory compiler with row redundancy. Memory_IP 55nm Bronze
FSF0G_W_SHUHVTRED UMC 55nm embedded flash and embedded E2PROM ultra low power split-gate process synchronous well bias feature HVT+uHVT periphery high density single port SRAM memory compiler with row redundancy. Memory_IP 55nm Bronze
FSF0I_A_SHHVT UMC 55nm CMOS Image Sensor 1P3M Process Single Port SRAM Memory Compiler with peri HVT Memory_IP 55nm Silver
FSF0I_A_SHHVTRED UMC 55nm CIS SP-SRAM with peri HVT and row redundancy Memory_IP 55nm Silver
FSF0U_A_SHHVT UMC 55nm ULP/LowK process Single-Port SRAM Memory_IP 55nm Silver Minus
 
FSF0U_A_SHHVTRED UMC 55nm ULP process , Single-Port SRAM with row repair and HVT Memory_IP 55nm Bronze
 
FSF0U_W_SHHVT UMC 55nm ULP/LowK Process Single-Port SRAM with well bias HVT Memory Compiler Memory_IP 55nm Silver Minus
FSF0U_W_SHHVTRED UMC 55nm ULP/LowK Process Single-Port SRAM with RED Well Biase Memory compiler Memory_IP 55nm Silver
FSF0U_W_SHUHVT UMC 55nm ULP/LowK Single-Port SRAM with Well Bias uHVT Memory_IP 55nm Silver Minus
FSF0U_W_SHUHVTRED UMC 55nm ULP/LowK Process Single-Port SRAM with well bias & RED Memory Compiler Memory_IP 55nm Bronze
FSF0V_A_SHHVT UMC 55EHV SP-SRAM compiler Memory_IP 55nm Silver
FSF0V_A_SHHVTRED UMC 55 EHV Process Single Port SRAM Memory Compiler with Row Redundancy Memory_IP 55nm Silver
FSH0L_D_SHHVT UMC 40nm LP Logic Process Single Port SRAM memory compiler using 213 bit -cell with peri-HVT Memory_IP 40nm Silver Minus
FSH0L_H_SHHVT UMC 40nm LP Logic Process ULL Single Port SRAM Memory Compiler using 213 bit-cell with peri-HVT Memory_IP 40nm Silver Minus
FSH0U_B_SHHVTRED UMC 40nm Low K Ultra Low Power Logic Process High-Density Single Port SRAM Compiler Memory_IP 40nm Contact Sales
FSH0U_L_SHHVT UMC 40nm uLP process ULL Single-Port SRAM Memory_IP 40nm Contact Sales
 
FSJ0C_D_SHHVT UMC 28nm HPC process synchronous HVT periphery high density single port SRAM memory compiler. Memory_IP 28nm Silver Minus
FSJ0P_D_SHHVT UMC 28HPC+ UHD SPSRAM compiler Memory_IP 28nm Contact Sales