Dual-Port SRAM

Updated On:2018-07-17
Gradation
Faraday IPs are rated according to the IPs’ maturity and customer acceptance. They are graded by the rules described as below,


Platinum P Five (5) productions verified
Gold G Mass production proven
Silver S Silicon proven, Formal release
Silver Minus S- Manufacturing onging
Bronze B Pre-Silicon release
 
Memory Compiler > Dual-Port SRAM
> 8TSRAM > High Density DPSRAM, 8TSRAM 
Cell Name Descriptions Type Process Gradation Literature
FSA0A_B_SJ UMC 0.18um Logic GII process standard synchronous high density dual port (2RW) SRAM memory compiler. Memory_IP 0.18um Gold
FSA0A_C_SJ UMC 0.18um Logic GII process standard synchronous high density dual port (2RW) SRAM memory compiler. Memory_IP 0.18um Platinum
FSA0M_A_SJ UMC 0.18um MM/RF process standard synchronous high density dual port SRAM memory compiler Memory_IP 0.18um Silver
FSC0C_A_SJ UMC 0.13um Al Standard performance process standard synchronous high density dual port SRAM compiler Memory_IP 0.13um Contact Sales
 
FSC0G_D_SJ UMC 0.13um Logic SP (FSG) process high density synchronous high density dual port (2RW) SRAM memory compiler. Memory_IP 0.13um Silver
FSC0H_D_SJ UMC 0.13um Logic HS (FSG) process high density synchronous dual port (2RW) SRAM memory compiler. Memory_IP 0.13um Platinum
FSC0H_D_SJBTI UMC 0.13um HS/FSG Logic process Synchronous high density dual port SRAM memory compiler with input wrapper mux Memory_IP 0.13um Gold
FSC0L_D_SJ UMC 0.13um Logic LL (FSG) process high density synchronous high density dual port (2RW) SRAM memory compiler. Memory_IP 0.13um Platinum
FSC0U_D_SJ UMC 0.13um HS/LL fusion (FSG) process high density synchronous high density dual port (2RW) SRAM memory compiler. Memory_IP 0.13um Silver
FSD0A_A_SJ UMC 90nm SP-RVT/Low-k process synchronous dual-port SRAM compiler Memory_IP 90nm Platinum
FSD0K_A_SJ UMC 90nm LL/RVT Synchronous high density dual-port SRAM memory compiler Memory_IP 90nm Silver
FSD0K_L_SJ UMC 90nm LL/RVT Low-k Logic Process Synchronouslow AC power dual-port SRAM Memory_IP 90nm Bronze
FSE0A_A_SJ UMC 65nm 1P10M 1.0v SP LowK Logic Process synchronous high density dual-port SRAM compiler (with row redundancy option) Memory_IP 65nm Silver
FSE0A_A_SJRED UMC 65nm logic SP-RVT and HVT (Lowk) Process synchronous, high density, dual-port SRAM compiler with the row redundancy option Memory_IP 65nm Silver Minus
FSE0K_A_SJ UMC 65nm Low Leakage RVT Logic Low_K process standard synchronous high density dual port SRAM memory compiler. Memory_IP 65nm Silver
FSE0K_A_SJBTI UMC 65nm Low Leakage RVT Logic Low_K process standard synchronous high density dual port SRAM memory compiler with bist testing interface. Memory_IP 65nm Silver
 
FSE0K_A_SJRED UMC 65nm Low Leakage RVT Logic Low_K process standard synchronous high density dual port SRAM memory compiler wiht redundancy elements. Memory_IP 65nm Silver
FSE0K_A_SJREDBTI UMC 65nm Low Leakage RVT Logic Low_K process standard synchronous high density dual port SRAM memory compiler with redundancy elements and bist testing interface. Memory_IP 65nm Silver
 
FSF0A_A_SJ UMC 55nm SP LowK Logic Process standard synchronous dual-port RAM memory compiler. Memory_IP 55nm Silver
FSF0A_A_SJRED UMC 55nm 1P10M 1.0V Standard Performance (SP) Lowk Logic Process synchronous, high density, dual-port SRAM with row redundancy option Memory_IP 55nm Silver
FSF0A_L_SJ UMC 55nm SP LowK Logic Process low power synchronous high density dual port SRAM memory compiler. Memory_IP 55nm Silver
FSF0A_L_SJRED UMC 55nm SP LowK Logic Process low power synchronous high density dual port SRAM memory compiler with redundancy. Memory_IP 55nm Silver
FSF0A_O_SJ 55 SP Dual Port SRAM compiler with 1P4M metal option Memory_IP 55nm Bronze
FSF0F_A_SJ UMC 55nm EFLASH Process Dual-Port SRAM Memory Compiler Memory_IP 55nm Bronze
FSF0F_A_SJRED UMC 55nm eFlash Process Dual-Port SRAM with Row redundancy Memory_IP 55nm Bronze
FSF0F_L_SJ UMC 55nm eFlash eFlash Dual-Port SRAM Memory Compiler Memory_IP 55nm Bronze
FSF0F_L_SJRED 55nm eFlash Dual-Port SRAM memory compiler with row redundancy Memory_IP 55nm Bronze
FSF0L_A_SJ UMC 55nm LP Logic Process Synchronous Dual-Port SRAM Memory Compiler Memory_IP 55nm Silver
FSF0L_A_SJRED UMC 55nm LP Logic Process Synchronous Dual-Port SRAM with RED feature Memory_IP 55nm Silver
FSF0L_L_SJ UMC 55nm LP process with PG Dual port SRAM compiler Memory_IP 55nm Contact Sales
 
FSF0L_L_SJRED UMC 55nm LP/Low-K Process with Row Redundancy Dual Port SRAM compiler Memory_IP 55nm Silver Minus
FSH0L_A_SJ UMC 40nm LP Logic Process standard synchronous high density dual port SRAM memory compiler. Memory_IP 40nm Silver
FSH0L_A_SJRED UMC 40nm Logic Process standard synchronous high density dual port SRAM memory compiler with redundancy Memory_IP 40nm Silver
FSH0L_C_SJ 40LP High density dual port SRAM compiler with Vss booster feature Memory_IP 40nm Silver Minus
FSH0L_C_SJRED UMC 40nm LP Logic Process Dual-Port SRAM memory compiler with redundancy Memory_IP 40nm Silver Minus
FSH0L_T_SJ UMC 40nm Low Power Process Dual-Port SRAM compiler with dual power rail Memory_IP 40nm Bronze
FSJ0C_A_SJ UMC 28nm HPC process Dual Port SRAM compiler Memory_IP 28nm Bronze
FSJ0C_A_SJR1 UMC 28nm HPC process Dual Port SRAM with row reapir Memory_IP 28nm Bronze
FSJ0C_L_SJHVT UMC 28nm HPC process standard synchronous high density dual port SRAM memory compiler. Memory_IP 28nm Bronze
FSJ0L_A_SJ UMC 28nm HLP/Low-k Dual-Port SRAM compiler Memory_IP 28nm Contact Sales
 
FSJ0L_A_SJR1 UMC 28nm HLP Logic Process ; Dual Port SRAM compiler with R1 Memory_IP 28nm Contact Sales
 
FSL0A_C_SJ UMC 153nm Mixed-Mode/Logic process standard synchronous high density dual port SRAM memory compiler. Memory_IP 0.153um Silver
FSR0B_D_SJ UMC 0.11um HS/ALE Logic Process standard synchronous High-density dual port SRAM memory compiler Memory_IP 0.11um Silver
FSR0F_C_SJ UMC 0.11um eFlash HS process; Dual Port SRAM compiler Memory_IP 0.11um Silver
FSR0H_D_SJ UMC 0.11um HS/RVT Logic process standard synchronous high density dual port SRAM memory compiler. Memory_IP 0.11um Silver
FSR0K_D_SJ UMC 0.11um LL/ALE (AL Enhancement) Logic Process standard synchronous high density dual port SRAM memory compiler. Memory_IP 0.11um Silver
FSR0L_D_SJ UMC 0.11um Low Leakage Logic process standard synchronous high density dual port SRAM memory compiler. Memory_IP 0.11um Gold
FSR0P_A_SJ UMC 0.11um eFlash LL process Dual port SRAM compiler Memory_IP 0.11um Bronze
 
FSR0T_D_SJ UMC 0.11um SP/AE (AL Advance Enhancement) Logic Process standard synchronous High-density dual port SRAM memory compiler. Memory_IP 0.11um Gold
 
Memory Compiler > Dual-Port SRAM
> 8TSRAM > High Density DPSRAM, 8TSRAM, Peri HVT 
Cell Name Descriptions Type Process Gradation Literature
FSF0V_A_SJHVT UMC 55nm EHV Dual Port SRAM Compiler with peri-HVT Memory_IP 55nm Silver Minus
FSF0V_A_SJHVTRED UMC 55nm EHV Dual Port SRAM compiler with peri_HVT Memory_IP 55nm Bronze
FSJ0C_A_SJHVT UMC 28nm HPC process Dual Port SRAM compiler Memory_IP 28nm Bronze
FSJ0C_A_SJHVTR1 UMC 28nm HPC process Dual Port SRAM compiler Memory_IP 28nm Bronze
FSJ0C_L_SJHVTR1 UMC 28HPC process standard synchronous high density dual port SRAM memory compiler. Memory_IP 28nm Bronze
FSJ0P_A_SJHVT UMC 28nm HPC+ process dual port SRAM memory compiler with HVT+RVT peripheral Memory_IP 28nm Contact Sales
 
 
Memory Compiler > Dual-Port SRAM
> 8TSRAM > High Density DPSRAM, 8TSRAM, Peri HVT, Power Gating 
Cell Name Descriptions Type Process Gradation Literature
FSH0L_L_SJHVTRED UMC 40NM Low-K Low Power synchronous Feature Dual Port SRAM memory compiler Memory_IP 40nm Contact Sales
 
 
Memory Compiler > Dual-Port SRAM
> 8TSRAM > High Density DPSRAM, 8TSRAM, Peri LVT 
Cell Name Descriptions Type Process Gradation Literature
FSH0L_A_SJLVT UMC 40nm LP Logic Process standard synchronous high density dual port SRAM memory compiler with LVT Memory_IP 40nm Silver
FSH0L_A_SJREDLVT UMC 40nm LP Logic Process standard synchronous high density dual port SRAM memory compiler with ROW redundancy with LVt peripheral Memory_IP 40nm Silver
FSH0L_C_SJLVT UMC 40nm LP Logic Process Dual-Port SRAM Memory Compiler with LVT peripheral Memory_IP 40nm Silver Minus
FSH0L_C_SJLVTRED UMC 40nm LP Logic Process Dual-Port SRAM memory compiler with redundancy and LVT peripheral Memory_IP 40nm Silver Minus
FSJ0C_A_SJLVT UMC 28nm HPC process Dual Port SRAM with LVT Memory_IP 28nm Bronze
FSJ0C_A_SJLVTR1 UMC 28nm HPC process Dual Port SRAM with row repair & LVT Memory_IP 28nm Bronze
FSJ0L_A_SJLVT UMC 28nm HLP Logic Process ; Dual Port SRAM compiler with LVT Memory_IP 28nm Contact Sales
 
 
Memory Compiler > Dual-Port SRAM
> 8TSRAM > High Density DPSRAM, 8TSRAM, Peri LVT, Power Gating 
Cell Name Descriptions Type Process Gradation Literature
FSH0L_L_SJLVT UMC 40nm LP LowK Logic Process ULL Dual-Port SRAM Memory Compiler with Peri-LVT Memory_IP 40nm Silver Minus
FSH0L_L_SJLVTRED UMC 40NM Low-K Low Power synchronous Feature Dual Port SRAM memory compiler Memory_IP 40nm Bronze
 
Memory Compiler > Dual-Port SRAM
> 8TSRAM > High Density DPSRAM, 8TSRAM, Power Gating 
Cell Name Descriptions Type Process Gradation Literature
FSH0L_L_SJ UMC 40nm LP Dual Port SRAM compiler with Sleep/Retention mode Memory_IP 40nm Silver Minus
FSH0L_L_SJRED UMC 40nm Low-K Low Power synchronous Feature Dual Port SRAM memory compiler Memory_IP 40nm Silver Minus