DDR

Updated On:2018-07-18
Gradation
Faraday IPs are rated according to the IPs’ maturity and customer acceptance. They are graded by the rules described as below,


Platinum P Five (5) productions verified
Gold G Mass production proven
Silver S Silicon proven, Formal release
Silver Minus S- Manufacturing onging
Bronze B Pre-Silicon release
 
Interface Solution > DDR
> DDR PHY - Command/Address > DDR2 - Command/Address 
Cell Name Descriptions Type Process Gradation Literature
FXDDR2A173HE0A DDR2/MDDR PHY CMD/ADDR BLOCK ; UMC 65nm 1.0V process with 2.5V device SP/RVT Lowk Logic Process Analog_IP 65nm Silver
FXDDR2A173HF0A DDR2/MDDR Combo PHY CMD ADDR block ; UMC 55nm SP/RVT Lowk Process with 2.5V device Analog_IP 55nm Silver
FXDDR2A174HE0A DDR2/MDDR PHY CMD/ADDR BLOCK for DIMM usage ; UMC 65nm 1.0V with 2.5V Device SP/RVT LowK Logic Process Analog_IP 65nm Silver
FXDDR2A174HF0A DDR2/MDDR PHY CMD/ADDR BLOCK for DIMM usage; UMC 55nm 1.0V with 2.5V device SP/RVT LowK Logic Process Analog_IP 55nm Silver
FXDDR2A200HC0H DDR2/MDDR Combo Command/Address Block ; UMC 0.13um HS/FSG Logic Process Analog_IP 0.13um Bronze
FXDDR2A200HE0L DDR2/DDR1/MDDR Combo Command/Address Block ; UMC 65nm LP/RVT LowK Logic Process Analog_IP 65nm Silver
FXDDR2A200HR0B Command/address block of 1:2 DDR2-PHY ; 0.11um HS/AE (AL Advanced Enhancement) Logic Process Analog_IP 0.11um Silver Minus
FXDDR2A200HR0H 1:2 DDR2/DDR1/MDDR combo PHY; UMC 0.11um HS/Cu Logic Process Analog_IP 0.11um Silver
 
FXDDRIIA171HC0H DDR2 PHY Command/Address Block ; UMC 0.13um HS/FSG Logic Process Analog_IP 0.13um Platinum
FXDDRIIA172HC0H DDR2 PHY Command/Address Block (for Chip Application); UMC 0.13um HS/FSG Logic Process Analog_IP 0.13um Silver
FXDDRIIA173HD0A_FTC DDR2-PHY command/address block for DRAM chip, BOAC ; UMC 90nm SP/RVT Low-K Logic Process Analog_IP 90nm Silver Minus
FXDDRIIA174HD0A DDR2-PHY Command/Address block; UMC 90nm SP/RVT Lowk Process Analog_IP 90nm Gold