DDR

Updated On:2018-07-24
Gradation
Faraday IPs are rated according to the IPs’ maturity and customer acceptance. They are graded by the rules described as below,


Platinum P Five (5) productions verified
Gold G Mass production proven
Silver S Silicon proven, Formal release
Silver Minus S- Manufacturing onging
Bronze B Pre-Silicon release
 
Interface Solution > DDR
> DDR PHY - Command/Address > LPDDR3 - Command/Address 
Cell Name Descriptions Type Process Gradation Literature
FXDDR4AFD612EWHJ0P Command/Address Block of DDR3/DDR4/LPDDR2/LPDDR3 Combo PHY supporting 2-rank application for Copper Pillar Bump Flip Chip Version ; UMC 28nm Logic and Mixed-Mode Low-K HPC+ Process Analog_IP 28nm Contact Sales
 
FXDDR4AFD612NSHJ0P Command/Address Block of DDR3/DDR4/LPDDR2/LPDDR3 Combo PHY supporting 2-rank application for Copper Pillar Bump Flip Chip Version ; UMC 28nm Logic and Mixed-Mode Low-K HPC+ Process Analog_IP 28nm Contact Sales
 
FXDDR4AFD622EWHJ0P Command/Address Block of DDR3/DDR4/LPDDR2/LPDDR3 Combo PHY supporting 2-rank application for Copper Pillar Bump Flip Chip Version ; UMC 28nm Logic and Mixed-Mode Low-K HPC+ Process Analog_IP 28nm Contact Sales
 
FXDDR4AFD622NSHJ0P Command/Address Block of DDR3/DDR4/LPDDR2/LPDDR3 Combo PHY supporting 2-rank application for Copper Pillar Bump Flip Chip Version ; UMC 28nm Logic and Mixed-Mode Low-K HPC+ Process Analog_IP 28nm Contact Sales
 
FXLPDDR3AW101HH0L LPDDR3-PHY Command/address block for LightCo ; UMC 40nm LP/RVT Logic Process Analog_IP 40nm Contact Sales