DDR

Updated On:2018-07-20
Gradation
Faraday IPs are rated according to the IPs’ maturity and customer acceptance. They are graded by the rules described as below,


Platinum P Five (5) productions verified
Gold G Mass production proven
Silver S Silicon proven, Formal release
Silver Minus S- Manufacturing onging
Bronze B Pre-Silicon release
 
Interface Solution > DDR
> DDR PHY - Data Block > LPDDR3 - Data Block 
Cell Name Descriptions Type Process Gradation Literature
FXDDR4DFD612EWHJ0C Data Block of DDR3/DDR4/LPDDR2/LPDDR3 Combo PHY for copper pillar bump Flip chip version ; UMC 28nm Logic and Mixed-Mode Low-K HPC Process Analog_IP 28nm Contact Sales
 
FXDDR4DFD612EWHJ0P Data Block of DDR3/DDR4/LPDDR2/LPDDR3 Combo PHY for copper pillar bump Flip chip version ; UMC 28nm Logic and Mixed-Mode Low-K HPC+ Process Analog_IP 28nm Contact Sales
 
FXDDR4DFD612NSHJ0C Data Block of DDR3/DDR4/LPDDR2/LPDDR3 Combo PHY for copper pillar bump Flip chip version ; UMC 28nm Logic and Mixed-Mode Low-K HPC Process Analog_IP 28nm Contact Sales
 
FXDDR4DFD612NSHJ0P Data Block of DDR3/DDR4/LPDDR2/LPDDR3 Combo PHY for copper pillar bump Flip chip version ; UMC 28nm Logic and Mixed-Mode Low-K HPC+ Process Analog_IP 28nm Contact Sales
 
FXDDR4DFD622NSHJ0P Data Block of DDR3/DDR4/LPDDR2/LPDDR3 Combo PHY for copper pillar bump Flip chip version ; UMC 28nm Logic and Mixed-Mode Low-K HPC+ Process Analog_IP 28nm Contact Sales
 
FXLPDDR3D16W101HH0L 40nm LPDDR3-PHY Data block for LightCo ; UMC 40nm LP/LVT Logic Process Analog_IP 40nm Contact Sales