PowerSlash Core Cell Library

Updated On:2018-07-16
Gradation
Faraday IPs are rated according to the IPs’ maturity and customer acceptance. They are graded by the rules described as below,


Platinum P Five (5) productions verified
Gold G Mass production proven
Silver S Silicon proven, Formal release
Silver Minus S- Manufacturing onging
Bronze B Pre-Silicon release
 
Logic Libraries > PowerSlash Core Cell Library
> 8-Track > 8T HVT PSK Library 
Cell Name Descriptions Type Process Gradation Literature
FSE0A_DHM_POWERSLASH
_CORE
UMC 65nm SP-HVT process Power slash cell library Library_Group 65nm Bronze
FSE0K_DHM_POWERSLASH
_CORE
UMC 65nm LL/HVT LowK Logic Process Powerslash core cell library Library_Group 65nm Bronze
FSF0A_DHS_POWERSLASH
_CORE
UMC 55nm SP-HVT LowK Process Power slash Cell Library (8-grid) Library_Group 55nm Bronze
FSF0F_DHS_POWERSLASH
_CORE
UMC 55nm eFlash/HVT LowK Logic Process 8-track POWERSLASH Core Library Library_Group 55nm Silver
FSF0G_DHE_POWERSLASH
_CORE
UMC 55nm uLP SST PROCESS HVT 8-track C60 standard cell Powerslash library Library_Group 55nm Bronze
FSF0L_DHS_POWERSLASH
_CORE
UMC 55nm LP/HVT LowK Logic Process 8-Tracks Powerslash Core Cell Library Library_Group 55nm Silver
FSF0U_DHA_POWERSLASH
_CORE
UMC 55nm ULP/HVT Low-K Logic Process Process 8-track Powerslash Cell Library (C90).W/O deep Nwell. Library_Group 55nm Silver
FSF0U_DHB_POWERSLASH
_CORE
UMC 55nm ULP/HVT Low-K Logic Process Process 8-track Powerslash Cell Library (C60). W/O deep Nwell Library_Group 55nm Silver
FSF0U_DHS_POWERSLASH
_CORE
UMC 55nm ULP/HVT Low-K Logic Process Process 8-track Powerslash Cell Library (C60) w/ Forward Bias. W/ deep Nwell. Library_Group 55nm Silver
FSF0U_DHU_POWERSLASH
_CORE
UMC 55nm ULP/HVT Low-K Logic Process Process 8-track Powerslash Cell Library (C90) w/ Forward Bias. W/ deep Nwell Library_Group 55nm Silver
FSR0F_D_POWERSLASH_C
ORE
UMC 0.11um eFlash/HS Process 8-track generic core cell library Library_Group 0.11um Silver