Clock

Updated On:2018-07-24
Gradation
Faraday IPs are rated according to the IPs’ maturity and customer acceptance. They are graded by the rules described as below,


Platinum P Five (5) productions verified
Gold G Mass production proven
Silver S Silicon proven, Formal release
Silver Minus S- Manufacturing onging
Bronze B Pre-Silicon release
 
Analog > Clock
> DDR DLL > 20M ~ 500M, DDR DLL 
Cell Name Descriptions Type Process Gradation Literature
FXDLL011HC0H Input 66M-133M Hz, output 66M-133M Hz, DDR DLL; UMC 0.13um Logic HS (FSG) process Analog_IP 0.13um Silver
FXDLL011HD0A Input 66M-200M Hz, output 66M-200M Hz, DDR DLL; UMC 90nm SP/RVT Low-K Logic Process. Analog_IP 90nm Gold
FXDLL300HC0H UMC 0.13um HS/FSG Process DLL-based cell that generates four-channel DQS with 13.5% ~ 36.6% timing delay for DDR1 SDRAM controller usage. Analog_IP 0.13um Silver
FXDLL300HR0B DLL-based cell that generates four-channel DQS with 13.5% ~ 36.6% timing delay for DDR1 SDRAM controller usage ;UMC 0.11um HS/AE (AL Advanced Enhancement) Logic Process Analog_IP 0.11um Silver
FXDLL310HD0A Input 200-333MHz, output 200-333MHz, DDR2 DLL; UMC 90nm SP/RVT Low-K logic process Analog_IP 90nm Bronze
FXDLL310HE0A Input 100-400MHz, output 100-400MHz, DDR2 DLL; UMC 65nm SP/RVT LowK Logic Process Analog_IP 65nm Silver Minus
FXDLL310HF0A Input 200-400MHz, output 200-400MHz, DDR2 DLL; UMC 55nm SP Low-K Logic Process Analog_IP 55nm Silver
FXDLL311HA0A Input 100M-200M Hz, output 100M-200M Hz, DDR DLL; 0.18um Logic GII process Analog_IP 0.18um Gold
FXDLL311HB0G Input 100M-200M Hz, output 100M-200M Hz, DDR DLL; 0.15um SP Logic process Analog_IP 0.15um Silver
FXDLL311HC0H Input 100M-200M Hz, output 100M-200M Hz, DDR DLL; 0.13um Logic HS (FSG) process Analog_IP 0.13um Platinum
FXDLL311HP0A Input 100M-200M Hz, output 100M-200M Hz, DDR DLL; UMC 0.162um Logic Process Analog_IP 0.162um Silver
 
FXDLL340HA0A Input 100M-150M Hz, output 100M-150M Hz, DDR DLL; 0.18um Logic GII process Analog_IP 0.18um Gold
FXDLL340HF0A Input 80-320MHz, output 6.25%~50% delay,80-320MHz, DDR2 DLL; UMC 55nm SP/RVT LowK Logic Process Analog_IP 55nm Silver
FXDLL350HC0H It is a 0.13?m HS DLL-based cell that generates three-channel DQS with 13.5% ~ 36.6% timing delay for DDR2 SDRAM controller usage. Analog_IP 0.13um Silver
FXDLL380HC0H DLL-based cell that generates two-channel DQS with 25% timing delay for DDR2 SDRAM controller usage ; UMC 0.13um HS/FSG Process Analog_IP 0.13um Bronze
FXDLL380HR0B DLL-based cell that generates two-channel DQS with 25% timing delay for DDR2 SDRAM controller usage ; UMC 0.11um HS/AE (AL Advanced Enhancement) Logic Process Analog_IP 0.11um Bronze
FXDLL380HR0H DLL-based cell that generates two-channel DQS with 25% timing delay for DDR2 SDRAM controller usage ; UMC 0.11um HS/RVT Logic Process Analog_IP 0.11um Bronze