Clock

Updated On:2018-07-22
Gradation
Faraday IPs are rated according to the IPs’ maturity and customer acceptance. They are graded by the rules described as below,


Platinum P Five (5) productions verified
Gold G Mass production proven
Silver S Silicon proven, Formal release
Silver Minus S- Manufacturing onging
Bronze B Pre-Silicon release
 
Analog > Clock
> Digitized DLL > 20M ~ 500M, Digitalized DLL 
Cell Name Descriptions Type Process Gradation Literature
FXADDLL200HH0L An ADDLL operate at 50MHz~210MHz. Supports slave delay line to generate per 1/32 UI programmable delay UMC 40nm LP/RVT Logic Process. Analog_IP 40nm Bronze
FXADDLL310HJ0L Input 333M-800MHz, output 333M-800MHz, all digital DLL with one-channel DQS delay range ; UMC 28nm HLP Process Analog_IP 28nm Contact Sales