MIPI

Updated On:2018-07-20
Gradation
Faraday IPs are rated according to the IPs’ maturity and customer acceptance. They are graded by the rules described as below,


Platinum P Five (5) productions verified
Gold G Mass production proven
Silver S Silicon proven, Formal release
Silver Minus S- Manufacturing onging
Bronze B Pre-Silicon release
 
Interface Solution > MIPI
> MIPI DPHY > MIPI DPHY Receiver 
Cell Name Descriptions Type Process Gradation Literature
FXDPHYRX12112HJ0C MIPI DPHY Reciever 80Mbps~2.5Gbps ; UMC 28nm HPC Logic Process Analog_IP 28nm Contact Sales
 
FXDPHYRX12112HJ0P MIPI DPHY Reciever 80Mbps~2.5Gbps ; UMC 28nm HPC+ Process Analog_IP 28nm Contact Sales
 
FXDPHYRX4111HJ0C MIPI Receiver, DPHY V1.1 RX ; UMC 28nm HPC process Analog_IP 28nm Contact Sales
 
FXDPHYRX4112HJ0C MIPI Receiver, DPHY V1.2 RX ; UMC 28nm HPC process Analog_IP 28nm Bronze
FXDPHYRX4112HJ0P MIPI RX 80Mbps~2.5Gbps ; UMC 28nm HPC+ process Analog_IP 28nm Contact Sales
 
FXDPHYRX4112NSHJ0P MIPI RX 80Mbps~2.5Gbps ; UMC 28nm HPC+ process Analog_IP 28nm Contact Sales
FXDPHYRX420HH0L MIPI Receiver 80Mbps-1.5Gbps; 40nm LP LowK Logic Process Analog_IP 40nm Silver
FXDPHYRX420HH0L_GPIO MIPI Receiver 80Mbps-1Gbps; 40nm LP LowK Logic Process Analog_IP 40nm Silver
FXDPHYRX4212HJ0C MIPI CSI Receiver 1G/ SLVDS 1G /HiSPi 1G, 1.8V/3.3V GPI 100MHz; UMC 28nm HPC Logic Process Analog_IP 28nm Contact Sales
 
FXDPHYRX8112HJ0C MIPI Receiver,DPHY RX V1.2; UMC 28nm HPC Logic and Mixed-Mode Process Analog_IP 28nm Contact Sales
 
FXDPHYTX4112NSHJ0P MIPI Transmitter 80Mbps~2.5Gbps; UMC 28nm HPC+ process Analog_IP 28nm Contact Sales
 
FXMPRX010HF0A MIPI Receiver 80Mbps ~ 1.5Gbps; UMC 55nm SP/RVT LowK Logic Process Analog_IP 55nm Silver Minus
FXMPRX010HH0L MIPI Receiver 80Mbps-1.5Gbps; 40nm LP LowK Logic Process Analog_IP 40nm Silver Minus
FXMPRX020HH0L MIPI Receiver 80Mbps-1Gbps; Combo PHY for MIPI & HiSPi & LVDS & SubLVDS,40nm LP LowK Logic Process Analog_IP 40nm Silver Minus
FXMPRX030HH0L MIPI Receiver 80Mbps-1Gbps; Combo PHY for MIPI & HiSPi & LVDS & SubLVDS,40nm LP LowK Logic Process, Two Lane. Analog_IP 40nm Silver Minus