2-Port SRAM

Updated On:2018-07-24
Gradation
Faraday IPs are rated according to the IPs’ maturity and customer acceptance. They are graded by the rules described as below,


Platinum P Five (5) productions verified
Gold G Mass production proven
Silver S Silicon proven, Formal release
Silver Minus S- Manufacturing onging
Bronze B Pre-Silicon release
 
Memory Compiler > 2-Port SRAM
> 8TSRAM > Asynchronous High Density 2PSRAM, 8TSRAM 
Cell Name Descriptions Type Process Gradation Literature
FG70A_A_RG UMC 0.45um Logic process standard gate array asynchronous embedded array high density two port (1R1W) SRAM memory compiler. Memory_IP 0.45um Silver
FS70A_B_RB UMC 0.5um Logic process standard asynchronous high density two port (1R1W) SRAM memory compiler. Memory_IP 0.5um Gold
FS80A_A_RB UMC 0.35um Logic process standard asynchronous high density two port (1R1W) SRAM memory compiler. Memory_IP 0.35um Gold
FS80A_B_RB UMC 0.35um Logic process standard asynchronous high density two port (1R1W) SRAM memory compiler. Memory_IP 0.35um Gold
 
Memory Compiler > 2-Port SRAM
> 8TSRAM > Asynchronous Low Power 2PSRAM, 8TSRAM 
Cell Name Descriptions Type Process Gradation Literature
FS70A_B_RW UMC 0.5um Logic process standard asynchronous low density low power two port (1R1W) SRAM memory compiler. Memory_IP 0.5um Gold
FS80A_A_RW UMC 0.35um Logic process standard asynchronous low density low power two port (1R1W) SRAM memory compiler. Memory_IP 0.35um Platinum
FS80A_B_RW UMC 0.35um Logic process standard asynchronous low density low power two port (1R1W) SRAM memory compiler. Memory_IP 0.35um Platinum
 
Memory Compiler > 2-Port SRAM
> 8TSRAM > High Density 2PSRAM, 8TSRAM 
Cell Name Descriptions Type Process Gradation Literature
FS80A_A_SB UMC 0.35um Logic process standard synchronous high density two port (1R1W) SRAM memory compiler. Memory_IP 0.35um Gold
FS80A_B_SB UMC 0.35um Logic process standard synchronous high density two port (1R1W) SRAM memory compiler. Memory_IP 0.35um Gold
 
Memory Compiler > 2-Port SRAM
> 8TSRAM > Low Power 2PSRAM, 8TSRAM 
Cell Name Descriptions Type Process Gradation Literature
FS80A_A_SW UMC 0.35um Logic process standard synchronous low density low power two port (1R1W) SRAM memory compiler. Memory_IP 0.35um Gold
FS80A_B_SW UMC 0.35um Logic process standard synchronous low density low power two port (1R1W) SRAM memory compiler. Memory_IP 0.35um Platinum
FS90A_B_SW UMC 0.25um Logic process standard synchronous low density low power two port (1R1W) SRAM memory compiler. Memory_IP 0.25um Platinum
 
Memory Compiler > 2-Port SRAM
> 8TSRAM > Synchronous High Density 2PSRAM, 8TSRAM peri HVT 
Cell Name Descriptions Type Process Gradation Literature
FSJ0C_A_SZHVTB4 UMC 28HPC Process Standard Synchronous High Density Two Port SRAM Memory Compiler. Memory_IP 28nm Bronze