Memory Compiler

Updated On:2018-07-18
Gradation
Faraday IPs are rated according to the IPs’ maturity and customer acceptance. They are graded by the rules described as below,


Platinum P Five (5) productions verified
Gold G Mass production proven
Silver S Silicon proven, Formal release
Silver Minus S- Manufacturing onging
Bronze B Pre-Silicon release
 
Memory Compiler > 1-Port SRAM
> 6TSRAM > High Density & Low Power 1PSRAM, 6TSRAM 
Cell Name Descriptions Type Process Gradation Literature
FSJ0C_L_SH UMC 28nm HPC Logic Process PG Single Port SRAM memory compiler Memory_IP 28nm Silver Minus
FSJ0C_L_SHR1 UMC 28nm HPC process standard synchronous high density single port low power SRAM memory compiler with row redundancy Memory_IP 28nm Bronze
 
Memory Compiler > 1-Port SRAM
> 6TSRAM > High Density & Low Power 1PSRAM, 6TSRAM, Peri HVT 
Cell Name Descriptions Type Process Gradation Literature
FSJ0C_L_SHHVT UMC 28nm HPC Logic Process PG Single-Port SRAM with HVT memory compiler Memory_IP 28nm Bronze
FSJ0C_L_SHHVTR1 UMC 28nm HPC process standard synchronous HVT periphery high density single port low power SRAM memory compiler with row redundancy Memory_IP 28nm Bronze
 
 
Memory Compiler > 1-Port SRAM
> 6TSRAM > High Density & Low Power 1PSRAM, 6TSRAM, Peri LVT 
Cell Name Descriptions Type Process Gradation Literature
FSJ0C_L_SHLVT UMC 28nm HPC Logic Process PG Single Port SRAM with LVT memory compiler Memory_IP 28nm Bronze
FSJ0C_L_SHLVTR1 UMC 28nm HPC process standard synchronous LVT periphery high density single port low power SRAM memory compiler with row redundancy Memory_IP 28nm Bronze
 
Memory Compiler > 1-Port SRAM
> 6TSRAM > High Density 1PSRAM, 6TSRAM 
Cell Name Descriptions Type Process Gradation Literature
FSJ0C_B_SH UMC 28nm Logic process standard synchronous RVT periphery high density single port SRAM memory compiler. Memory_IP 28nm Bronze
FSJ0C_B_SHR1 UMC 28nm Logic process standard synchronous RVT periphery high density single port SRAM memory compiler with row redundancy. Memory_IP 28nm Bronze
FSJ0C_D_SH UMC 28nm HPC Logic Process Ultra High Density Single-Port SRAM Memory Compiler Memory_IP 28nm Silver Minus
FSJ0G_B_SH UMC 28nm HPM process standard synchronous high density single port SRAM memory compiler Memory_IP 28nm Silver Minus
FSJ0L_B_SH High Density Single Port SRAM, UMC 28nm HLP process Memory_IP 28nm Silver Minus
FSJ0L_B_SHC1 UMC 28nm HLP process standard synchronous high density single port SRAM memory compiler. Memory_IP 28nm Contact Sales
 
FSJ0L_B_SHR1 UMC 28nm HLP standard synchronous high density single port SRAM memory compiler. Memory_IP 28nm Bronze
FSJ0L_B_SHR1C1 UMC 28nm HLP process standard synchronous High density single port SRAM memory compiler. Memory_IP 28nm Contact Sales
 
 
Memory Compiler > 1-Port SRAM
> 6TSRAM > High Density 1PSRAM, 6TSRAM, Peri H/RVT 
Cell Name Descriptions Type Process Gradation Literature
FSJ0C_D_SHHVTR1 UMC 28nm HPC Process Synchronous HVT/RVT Periphery High Density Single Port SRAM Memory Compiler with Row Redundancy Memory_IP 28nm Bronze
 
Memory Compiler > 1-Port SRAM
> 6TSRAM > High Density 1PSRAM, 6TSRAM, Peri HVT 
Cell Name Descriptions Type Process Gradation Literature
FSJ0C_D_SHHVT UMC 28nm HPC process synchronous HVT periphery high density single port SRAM memory compiler. Memory_IP 28nm Silver Minus
FSJ0P_D_SHHVT UMC 28HPC+ UHD SPSRAM compiler Memory_IP 28nm Contact Sales
 
 
Memory Compiler > 1-Port SRAM
> 6TSRAM > High Density 1PSRAM, 6TSRAM, Peri LVT 
Cell Name Descriptions Type Process Gradation Literature
FSJ0C_B_SHLVT UMC 28nm Logic process standard synchronous LVT periphery high density single port SRAM memory compiler. Memory_IP 28nm Silver Minus
FSJ0C_B_SHLVTR1 UMC 28nm Logic process standard synchronous LVT periphery high density single port SRAM memory compiler. Memory_IP 28nm Bronze
FSJ0C_D_SHLVT UMC 28nm HPC process synchronous LVT periphery high density single port SRAM memory compiler. Memory_IP 28nm Bronze
FSJ0C_D_SHLVTR1 UMC 28nm HPC Process Synchronous LVT/RVT Periphery High Density Single Port SRAM Memory Compiler with Row Redundancy Memory_IP 28nm Contact Sales
FSJ0L_B_SHLVT UMC 28nm HLP Logic process LVT standard synchronous high density single port SRAM memory compiler. Memory_IP 28nm Bronze
FSJ0L_B_SHLVTC1 UMC 28nm HLP process standard LVT synchronous high density single port SRAM memory compiler. Memory_IP 28nm Contact Sales
 
FSJ0L_B_SHLVTR1 UMC 28nm HLP Logic process LVT standard synchronous high density single port SRAM memory compiler. Memory_IP 28nm Bronze
FSJ0L_B_SHLVTR1C1 UMC 28nm HLP process LVT standard synchronous high density single port SRAM memory compiler. Memory_IP 28nm Contact Sales
 
 
Memory Compiler > 1-Port SRAM
> 6TSRAM > Ultra High Density 1PSRAM, 6TSRAM 
Cell Name Descriptions Type Process Gradation Literature
FSJ0C_D_SHR1 UMC 28nm HPC Logic Process Ultra High Density Single-Port SRAM Memory Compiler with Row Redundancy Memory_IP 28nm Contact Sales
 
 
Memory Compiler > 1-Port SRAM
> 6TSRAM > Ultra High Speed 1PSRAM, 6T SRAM 
Cell Name Descriptions Type Process Gradation Literature
FSJ0C_A_SE UMC 28nm HPC Process Ultra High Speed Single-Port SRAM memory compiler Memory_IP 28nm Bronze
 
Memory Compiler > 1-Port SRAM
> 6TSRAM > Ultra High Speed 1PSRAM, 6T SRAM, Peri LVT 
Cell Name Descriptions Type Process Gradation Literature
FSJ0C_A_SELVT UMC 28nm HPC Process Ultra High Speed Single-Port SRAM Memory Compiler Memory_IP 28nm Silver Minus