Memory Compiler

Updated On:2018-07-16
Faraday IPs are rated according to the IPs’ maturity and customer acceptance. They are graded by the rules described as below,

Platinum P Five (5) productions verified
Gold G Mass production proven
Silver S Silicon proven, Formal release
Silver Minus S- Manufacturing onging
Bronze B Pre-Silicon release
Memory Compiler > Dual-Port SRAM
> 8TSRAM > High Density DPSRAM, 8TSRAM, Peri LVT 
Cell Name Descriptions Type Process Gradation Literature
FSJ0C_A_SJLVT UMC 28nm HPC process Dual Port SRAM with LVT Memory_IP 28nm Bronze
FSJ0C_A_SJLVTR1 UMC 28nm HPC process Dual Port SRAM with row repair & LVT Memory_IP 28nm Bronze
FSJ0L_A_SJLVT UMC 28nm HLP Logic Process ; Dual Port SRAM compiler with LVT Memory_IP 28nm Contact Sales