Logic Libraries

Updated On:2018-07-20
Gradation
Faraday IPs are rated according to the IPs’ maturity and customer acceptance. They are graded by the rules described as below,


Platinum P Five (5) productions verified
Gold G Mass production proven
Silver S Silicon proven, Formal release
Silver Minus S- Manufacturing onging
Bronze B Pre-Silicon release
 
Logic Libraries > IO Cell Library
> Analog ESD IO Library > True 3.3V Analog ESD IO Library 
Cell Name Descriptions Type Process Gradation Literature
FOJ0C_ORS18_T33_ANAL
OGESD_IO
UMC 28nm Logic and Mixed-Mode HPC Process 3.3V Analog ESD IO cell Library Library_Group 28nm Bronze
FOJ0C_QRS18_T33_ANAL
OGESD_IO
UMC 28nm Logic and Mixed-Mode HPC Process 3.3V Analog ESD IO cell PG_lib Library Library_Group 28nm Bronze
FOJ0L_ORS18_T33_ANAL
OGESD_IO
UMC 28nm HLP Logic Process, 3.3V Analog ESD IO cell Library Library_Group 28nm Silver
FOJ0L_QRS25_T33_ANAL
OGESD_IO
UMC 28nm LP/RVT Logic Process, 3.3V Analog ESD IO cell Library (using 2.5V overdrive 3.3V MOS) Library_Group 28nm Bronze
FOJ0P_ORS18_T33_ANAL
OGESD_IO
UMC 28nm Logic and Mixed-Mode HPC+ Process 3.3V Analog ESD IO cell Library Library_Group 28nm Contact Sales
 
FOJ0P_QRS18_T33_ANAL
OGESD_IO
UMC 28nm Logic and Mixed-Mode HPC+ Process 3.3V Analog ESD IO cell PG_lib Library Library_Group 28nm Bronze