Analog

Updated On:2018-07-20
Gradation
Faraday IPs are rated according to the IPs’ maturity and customer acceptance. They are graded by the rules described as below,


Platinum P Five (5) productions verified
Gold G Mass production proven
Silver S Silicon proven, Formal release
Silver Minus S- Manufacturing onging
Bronze B Pre-Silicon release
 
Analog > A/D Converter
> Audio ADC > 10Bit Audio ADC 
Cell Name Descriptions Type Process Gradation Literature
FXADC350HH0L 10-bit 50Msps SAR ADC, UMC 40nm LP/Low-K LVT process Analog_IP 40nm Bronze
 
Analog > A/D Converter
> Pipelined ADC > 10Bit Pipelined ADC 
Cell Name Descriptions Type Process Gradation Literature
FXADC010HH0L 1.1V/2.5V 10Bits 80MSPS Pipelined ADC; UMC 40nm LP/RVT Logic Process Analog_IP 40nm Silver
FXADC011HH0L 1.1V/3.3V 10Bits 45MSPS Pipelined ADC; UMC 40nm LP/RVT LowK Logic Process Analog_IP 40nm Bronze
 
Analog > A/D Converter
> SAR ADC > 10Bit SAR ADC 
Cell Name Descriptions Type Process Gradation Literature
FXADC1402HH0L 10 bit 1MSPS A/D Converter; UMC 40 nm LP/RVT Low-K Logic Process Analog_IP 40nm Contact Sales
 
FXADC1402HH0L_FTCM8A 10 bits 1MSPS SAR ADC ; UMC 40nm LP/RVT Logic Process Analog_IP 40nm Silver Minus
FXADC1403HH0L 10 bit 1MSPS A/D Converter; UMC 40 nm LP/RVT Low-K Logic Process Analog_IP 40nm Contact Sales
 
FXADC883HH0L 10-BIT 1 MSPS 8-TO-1 SAR ADC WITH INTERNAL TEMPERATURE SENSOR,UMC 40nm LP/RVT LowK Logic Process Analog_IP 40nm Contact Sales
 
 
Analog > A/D Converter
> SAR ADC > 12Bit SAR ADC 
Cell Name Descriptions Type Process Gradation Literature
FXADC2502HH0L a 12-bit 1MSPS SAR-ADC on UMC 40nm LP, with 10-channel GPIO integrated Analog_IP 40nm Bronze
 
Analog > A/D Converter
> SAR ADC > 8Bit SAR ADC 
Cell Name Descriptions Type Process Gradation Literature
FXADC183HH0L 8 bit 70KSPS SAR ADC; UMC 40nm LP/HVT LowK Logic Process Analog_IP 40nm Silver
 
Analog > Analog Front Ends
> Image Processing AFE 
Cell Name Descriptions Type Process Gradation Literature
FXAFE030HH0L FXAFE030HH0L is an Analog Front End IP for image processing applications. FXAFE030HH0L is fabricated in UMC 40 nm logic LP/HVT Low-K process to implement a signal processing solution for scanners, video and imaging applications. Analog_IP 40nm Silver
 
Analog > Clock
> All Digital Delay Line > 20M ~ 500M, All Digital Delay Line 
Cell Name Descriptions Type Process Gradation Literature
FXDCDL201HH0L Input 50M-210MHz, output 50M-210MHz. An all digital slave delay line of FXADDLL200HH0L to generate Programmable delay per 1/32 UI delay line UMC 40nm LP Logic Process Analog_IP 40nm Bronze
 
Analog > Clock
> All Digital Delay Line > 500M ~ 1G, All Digital Delay Line 
Cell Name Descriptions Type Process Gradation Literature
FXDCDL331HH0L Input 360M-720MHz, output 360M-720MHz, all digital slave delay line of FXADDLL330HH0L to generate programmable delay in period of FREF,UMC 40nm LP Process Analog_IP 40nm Bronze
FXDCDL351HH0L Input 360M-720MHz, output 360M-720MHz, all digital slave delay line of FXADDLL330HH0L to generate programmable delay in period of FREF, UMC 40nm LP Process Analog_IP 40nm Bronze
 
Analog > Clock
> All Digital Delay Line > over 1G, All Digital Delay Line 
Cell Name Descriptions Type Process Gradation Literature
FXDCDL341HH0L Input 800M-1600MHz, output 800M-1600MHz, all digital slave delay line of FXADDLL340HJ0G to generate 100% delay in period of FREF,UMC 40nm Logic Process Analog_IP 40nm Bronze
FXDCDL342HH0L Input 800M-1600MHz, output 800M-1600MHz, all digital slave delay line of FXADDLL340HJ0G to generate 100% delay in period of FREF,UMC 40nm Logic Process . Analog_IP 40nm Bronze
FXDCDL343HH0L Input 800M-1600MHz, output 800M-1600MHz, all digital slave delay line of FXADDLL340HJ0G to generate 100% delay in period of FREF,UMC 40nm Logic Process Analog_IP 40nm Bronze
FXDCDL344HH0L Input 400M-1600MHz, output 400M-1600MHz, all digital slave delay line of FXADDLL340HH0L to generate 25% delay in period of FREF, UMC 40nm LP/RVT Logic Process. Analog_IP 40nm Bronze
 
Analog > Clock
> DLL > 20M ~ 500M, DLL 
Cell Name Descriptions Type Process Gradation Literature
FXDLL340HH0L Input 80MHz-280MHz, DQS delay 3.125%-50% of FREF period, UMC 40nm LP/RVT Low-K logic process. Analog_IP 40nm Silver Minus
FXDLL344HH0L Input 80MHz-440MHz, DQS delay 1/32 and 1/16 of FREF period, UMC 40nm LP/RVT Low-K logic process. Analog_IP 40nm Bronze
 
Analog > Clock
> Digitized DLL > 20M ~ 500M, Digitalized DLL 
Cell Name Descriptions Type Process Gradation Literature
FXADDLL200HH0L An ADDLL operate at 50MHz~210MHz. Supports slave delay line to generate per 1/32 UI programmable delay UMC 40nm LP/RVT Logic Process. Analog_IP 40nm Bronze
 
Analog > Clock
> Digitized DLL > 500M ~ 1G, Digitalized DLL 
Cell Name Descriptions Type Process Gradation Literature
FXADDLL310HH0L Input 333M-800MHz, output 333M-800MHz, all digital DLL with one-channel DQS delay range ; UMC 40nm LP/RVT LowK Logic Process Analog_IP 40nm Silver Minus
FXADDLL330HH0L An ADDLL operate at 300MHz~600MHz. Output 0-180 degree Phase adjustment range. Delay adjustment resolution <= 1% of reference clock UMC 40nm LP/RVT Logic Process. Analog_IP 40nm Silver
FXADDLL350HH0L Input 360M-720M Hz, output 360M-720M Hz, DLL;Output 0-180 degree Phase adjustment range. UMC 40nm LP process. Analog_IP 40nm Bronze
 
Analog > Clock
> Digitized DLL > over 1G, Digitalized DLL 
Cell Name Descriptions Type Process Gradation Literature
FXADDLL340HH0L Input 800M-1600MHz, output 800M-1600MHz, all digital DLL for DDR4 SDRAM controller usage, supports slave delay line to generate 25%/50%/100% delay in period of FREF,UMC 40nm Logic Process. Analog_IP 40nm Bronze
 
Analog > Clock
> Oscillator 
Cell Name Descriptions Type Process Gradation Literature
FXLCOSC012HH0L XTAL LESS for USB3.0 ; UMC 40nm LP/RVT Logic Process Analog_IP 40nm Bronze
FXOSC002HH0L Internal-RC, frequency 1.8432MHz or 2.4576MHz, Input 1.045V-1.155V, VBG=0.8V Oscillator. UMC 40nm LP/RVT Logic Process. Analog_IP 40nm Silver Minus
FXOSC032HH0L Internal-R,output frequency 32 KHz, Input 0.99V-1.21V Oscillator. UMC 40nm LP/RVT Logic Process. Analog_IP 40nm Silver
FXOSC048HH0L InternalRC OSC, optional outout frequency 48MHz/24MHz/16MHz/12MHz, input VBG=0.8V; UMC 40nm LP/RVT Logic Process Analog_IP 40nm Silver Minus
FXOSC054HH0L Internal RC OSC, optional outout frequency 54MHz/27MHz/18MHz/13.5MHz, input VBG=0.8V; UMC 40nm LP/RVT Logic Process Analog_IP 40nm Bronze
 
Analog > Clock
> Others 
Cell Name Descriptions Type Process Gradation Literature
FXS2D101HH0L IP name: FXS2D101HH0L Area: 300um*300um Analog_IP 40nm Silver
 
Analog > Clock
> PLL > 20M ~ 500M, Generic PLL 
Cell Name Descriptions Type Process Gradation Literature
FXPLL010HH0L Input 10-50M Hz, output 10-200M Hz, frequency synthesizable PLL; UMC 40nm LP/RVT Logic Process Analog_IP 40nm Silver
FXPLL010HH0L_FTC Input 10-50M Hz, output 10-200M Hz, frequency synthesizable PLL; UMC 40nm LP/RVT Logic Process(Note:same schematic with FXPLL010HH0L, but Poly Density Errors are waived in layout for 40% area reduced.) Analog_IP 40nm Bronze
FXPLL125HH0L Input 12M Hz, output clock1 540M Hz and output clock2 120M Hz, PLL; UMC 40nm LP/RVT Low-K Logic Process Analog_IP 40nm Silver Minus
FXPLL134HH0L miniPLL (TM) Phase-Locked Loop (PLL) with an operating frequency range of between 250 MHz and 500 MHz ; UMC 40nm LP/RVT Logic Process Analog_IP 40nm Bronze
FXPLL360HH0L_LTE2 Input 25M~440MHz, output 267M-533M, 200M-400M and 160M-320M, frequency synthesizable PLL; UMC 40nm LP/RVT Logic Process Analog_IP 40nm Contact Sales
 
FXPLL362HH0L Input 200MHz - 400MHz, output clock_1X 200MHz - 400MHz, output clock_2X 400MHz - 800MHz, output clock_4X 800MHz-1600MHz,frequency synthesizable PLL;UMC 40nm LP/RVT LowK Logic process Analog_IP 40nm Silver Minus
 
Analog > Clock
> PLL > 500M ~ 1G, Generic PLL 
Cell Name Descriptions Type Process Gradation Literature
FXPLL360HH0L Input 25M-66M Hz, output 400M-800M Hz, frequency synthesizable PLL; UMC 40nm LP/RVT Logic Process Analog_IP 40nm Silver
FXPLL510HH0L_DPHY Input 6M-27M Hz, output 10M-850M Hz, frequency synthesizable PLL; UMC 40nm Logic LP RVT and LVT process Analog_IP 40nm Silver
FXPLLLV362HH0L This IP for DDR4, Input 200MHz - 800MHz, output clock_1X 200MHz - 800MHz, output clock_2X 400MHz - 1600MHz, output,frequency synthesizable PLL; UMC 40nm LP Logic Process Analog_IP 40nm Contact Sales
 
Analog > Clock
> PLL > over 1G, Generic PLL 
Cell Name Descriptions Type Process Gradation Literature
FXPLL110HH0L Input 10M-200M Hz, output 62.5M-1G Hz, frequency synthesizable PLL; UMC 40 nm LP/RVT Low-K Logic Process Analog_IP 40nm Silver
FXPLL120HH0L Input 20M-200M Hz, output 500M-1G Hz, frequency synthesizable PLL; UMC 40nm LP/RVT LowK Logic Process Analog_IP 40nm Silver
 
Analog > Clock
> SSCG > 500M ~ 1G, SSCG 
Cell Name Descriptions Type Process Gradation Literature
FXSSCG360HH0L Input clock:25~66MHz, output clock range:400 ~ 800 MHz wide-range SSCG; UMC 40nm LP/RVT process. Analog_IP 40nm Silver
 
Analog > Clock
> SSCG > over 1G, SSCG 
Cell Name Descriptions Type Process Gradation Literature
FXSSCG602HH0L Input clock range:5 ~ 1280 MHz, output clock range:15.625 ~ 2000 MHz wide-range SSCG; UMC UMC 40nm LP/LVT LowK Logic Process Analog_IP 40nm Silver
FXSSCG603HH0L Input clock:8MHz, output clock range:720 ~ 1680 MHz wide-range SSCG; UMC 40nm LP process. Analog_IP 40nm Silver
 
Analog > Codecs ADDA
> SigmaDelta ADDA > 24Bit Audio CODEC 
Cell Name Descriptions Type Process Gradation Literature
FXADDA302HH0L 24bit 96KHz Audio Codec ; UMC 40nm Logic LP/HVT 2.5OD3.3 process Analog_IP 40nm Silver
FXADDA308HH0L 24bit 96KHz Audio Codec ; UMC 40nm Logic LP/HVT 2.5OD3.3 process Analog_IP 40nm Silver Minus
 
Analog > Codecs ADDA
> SigmaDelta ADDA > 24Bit High Performance Stereo Audio CODEC 
Cell Name Descriptions Type Process Gradation Literature
FXADDA300HH0L UMC 40nm high performance stereo audio codec with highly integrated analog functionality system Analog_IP 40nm Silver
 
Analog > Codecs ADDA
> SigmaDelta ADDA > 24Bit Sampled Mono Audio CODEC 
Cell Name Descriptions Type Process Gradation Literature
FXADDA301HH0L 24-Bit Mono Audio CODEC with speaker driver. UMC 40nm LP LowK Logic Process. Analog_IP 40nm Silver
 
Analog > Codecs ADDA
> SigmaDelta ADDA > High Performance Mono Audio CODEC 
Cell Name Descriptions Type Process Gradation Literature
FXADDA600HH0L UMC 40nm high performance mono audio codec with highly integrated analog functionality system Analog_IP 40nm Contact Sales
 
 
Analog > D/A Converter
> Video DAC > 10Bit 1-Channel Video DAC 
Cell Name Descriptions Type Process Gradation Literature
FXDAC021HH0L 10bit 150MSPS 1-ch Video DAC,UMC 40nm LP/HVT Low-K process Analog_IP 40nm Silver
FXDAC022HH0L 10bit 150MSPS 1-ch Video DAC,UMC 40nm LP/RVT Low-K proces Analog_IP 40nm Silver Minus
 
Analog > D/A Converter
> Video DAC > 10Bit 3-Channel Video DAC 
Cell Name Descriptions Type Process Gradation Literature
FXDAC032HH0L 10bit 150MSPS 3-ch Video DAC,UMC 40nm LP/RVT Low-K process Analog_IP 40nm Silver Minus
 
Analog > Data Converter
> TDC Converter 
Cell Name Descriptions Type Process Gradation Literature
FXDTDC040HH0L A 256bit thermocode timing to digital converter with process monitor and calibration, input 400MHz, timing resolution 30ps, UMC 40nm LP/LVT/RVT Low-K logic process Analog_IP 40nm Contact Sales
 
FXTDC011HH0L_25 A 2.5V 1.0 KSPS 0.25C/LSB 10-bit Temperature-to-Digital converter.8-bit trimming bits from register input, by UMC 40nm LP process Analog_IP 40nm Contact Sales
 
 
Analog > Others
> Customization Design 
Cell Name Descriptions Type Process Gradation Literature
FZCC100HH0L TypeC CC channel for USBPD ; UMC 40NM LP Low-K process. Analog_IP 40nm Contact Sales
 
Analog > Power
> Band Gap 
Cell Name Descriptions Type Process Gradation Literature
FXBG010HH0L Input 2V-3.6V, VBG=1.23V BandGap; UMC 40nm LP/RVT LowK Logic Process Analog_IP 40nm Bronze
FXBG011HH0L Input 2.5V, VBG=1.23V BandGap; UMC 40nm LP/RVT LowK Logic Process Analog_IP 40nm Bronze
FXBG020HH0L Input 1.1V, VBG=0.8V, Band Gap,UMC 40nm LP/RVT LowK Logic Process Analog_IP 40nm Bronze
FXBG220HH0L Input 1.1V, VBG=0.48V, Band Gap,UMC 40nm LP/RVT LowK Logic Process Analog_IP 40nm Bronze
 
Analog > Power
> Linear Regulator 
Cell Name Descriptions Type Process Gradation Literature
FXREG010HH0L 3.3V to 2.5V with 50mA driving capability; Linear Regulator; UMC 40nm LP/RVT LowK Logic Process Analog_IP 40nm Silver
FXREG011HH0L 3.3V to 2.5V with 110mA driving capability with external capacitor(use trimming PADs) Linear Regulator; UMC 40nm LP/RVT LowK Logic Process Analog_IP 40nm Silver
FXREG011HH0L_150MA 3.3V to 2.5V Regulator with 150mA; UMC 40nm LP/RVT LowK Logic Process Analog_IP 40nm Contact Sales
 
FXREG012HH0L 3.3V to 1.8V with 150mA driving capability; Linear Regulator; UMC 40nm LP/RVT LowK Logic Process Analog_IP 40nm Silver
FXREG014HH0L 3.3v to 2.5v with 30mA driving capability without external capacitor (Cap-less), use trimming PADs; Linear Regulator; UMC 40nm LP/RVT LowK Logic process Analog_IP 40nm Bronze
FXREG020HH0L 3.3V to 1.1V with 150mA driving capability; Linear Regulator; UMC 40nm LP/RVT LowK Logic Process Analog_IP 40nm Bronze
FXREG020HH0L_200MA 3.3v to 1.1v/200mA REG, Linear Regulator, UMC 40nm LP/RVT LowK Logic Process Analog_IP 40nm Contact Sales
 
FXREG020HH0L_300MA 3.3v to 1.1v/300mA REG, Linear Regulator, UMC 40nm LP/RVT LowK Logic Process Analog_IP 40nm Contact Sales
 
FXREG020HH0L_PLL 3.3V to 1.1V with 30mA driving capability; Linear Regulator; UMC 40nm LP/RVT LowK Logic Process Analog_IP 40nm Contact Sales
 
FXREG021HH0L 1.8V and 1.2V input, loading 360mA, 1.1V output with VBG=0.88V Regulator with BYPASS mode;UMC 40nm LP/RVT LowK Logic Process Analog_IP 40nm Silver Minus
FXREG024HH0L 3.3v to 1.1v/200mA REG, Linear Regulator, UMC 40nm LP/RVT LowK Logic process Analog_IP 40nm Silver
FXREG100HH0L 3.3V to 1.1V with 150mA driving capability; High accuracy Non-trim Linear Regulator; UMC 40nm LP/RVT LowK Logic Process Analog_IP 40nm Silver
FXREG200HH0L 3.3V to 1.1V with 100mA driving capability; Fast Transient Linear Regulator; UMC 40nm LP/RVT LowK Logic Process Analog_IP 40nm Silver
FXREG230HH0L 3.3V to 1.1V/100mA REG; Linear Regulator; UMC 40nm LP/RVT LowK Logic Process Analog_IP 40nm Bronze
FXREG231HH0L 3.3V to 1.1V /50mA REG; Linear Regulator; UMC 40nm LP/RVT LowK Logic Process Analog_IP 40nm Bronze
FXREG300HH0L 3.3V to 2.5V with 5mA driving capability; Capacitor-free Linear Regulator; UMC 40nm Logic/Mixed-Mode Low Power Process Analog_IP 40nm Bronze
 
Analog > Power
> PWM Regulator 
Cell Name Descriptions Type Process Gradation Literature
FXPWM011HH0L Boosting voltage from 3.3V to 5V, 100mA driving capability, Pulse Width Modulator; UMC 40nm Logic LP/RVT Low-K process. Analog_IP 40nm Bronze
FXPWM021HH0L 3.3V to 1.1V / 600mA PWM, Switching Regulator, UMC 40nm LP/RVT LowK Logic Process Analog_IP 40nm Bronze
 
Analog > Power
> Power on Reset 
Cell Name Descriptions Type Process Gradation Literature
FXPORK235HH0L Vrr=0.8V,Vfr=0.65V,input VCC=1.1V, 1.1V Power On Reset; UMC 40nm LP/RVT LowK Logic Process Analog_IP 40nm Silver
FXPORKH025HH0L 2.5V Power On Reset, Vrr=1.90 without Vfr, UMC 40nm LP/RVT LowK Logic Process Analog_IP 40nm Bronze
FXPORKH075HH0L Vrr=2.0V Vfr=1.9V, VCC3I=2.5V, 2.5V Power On Reset;special request; UMC 40nm LP/RVT LowK Logic Process Analog_IP 40nm Silver Minus
FXPORKHR025HH0L 3.3V Power On Reset, Vrr=1.90 without Vfr, UMC 40nm LP/RVT LowK Logic Process Analog_IP 40nm Silver Minus
FXPORKLH035HH0L Vrr=2.33V Vfr=2.26V, input VCCK=1.0V VCC3IO=3.3V, 3.3V Power On Reset;special request; UMC 40nm LP/RVT LowK Logic Process Analog_IP 40nm Silver
FXPORKLH230HH0L Input VCC3V=3.3V, 3.3V Power On Reset; UMC 40nm LP Logic Process Analog_IP 40nm Silver
FXPORKLH530HH0L Input VCC=1.1V& VCC3V=3.3V, 1.1/3.3V Power On Reset; UMC 40nm LP Logic Process Analog_IP 40nm Silver
 
Analog > Power
> Voltage Detector 
Cell Name Descriptions Type Process Gradation Literature
FXVDT010HH0L Power input 3.3v, 1-level voltage detector, UMC 40nm LP/RVT LowK Logic process Analog_IP 40nm Bronze
FXVDT013HH0L Power input 1.1v, 4-level voltage detector, UMC 40nm LP/HVT LowK Logic process Analog_IP 40nm Silver
FXVDT021HH0L 4-Level Voltage Detector for USB-OTG ; UMC 40nm 2.5V overdrive 3.3V device LP/RVT Logic Process Analog_IP 40nm Silver