Logic Libraries

Updated On:2018-07-22
Gradation
Faraday IPs are rated according to the IPs’ maturity and customer acceptance. They are graded by the rules described as below,


Platinum P Five (5) productions verified
Gold G Mass production proven
Silver S Silicon proven, Formal release
Silver Minus S- Manufacturing onging
Bronze B Pre-Silicon release
 
Logic Libraries > IO Cell Library
> Analog ESD IO Library 
Cell Name Descriptions Type Process Gradation Literature
FOH0L_PRS11_T11_ANAL
OGESD_LOWC_IO
1.1V analog ESD IO cells with low capacitor for UMC 40LP process Library_Group 40nm Contact Sales
 
 
Logic Libraries > IO Cell Library
> Analog ESD IO Library > True 1.1V Analog ESD IO Library 
Cell Name Descriptions Type Process Gradation Literature
FOH0L_PRS25_T11_ANAL
OGESD_IO
UMC 40nm LP/RVT Logic Process, 1.1V Analog ESD IO cell Library Library_Group 40nm Silver
 
Logic Libraries > IO Cell Library
> Analog ESD IO Library > True 1.8V Analog ESD IO Library 
Cell Name Descriptions Type Process Gradation Literature
FOH0L_PRS25_T18_ANAL
OGESD_LOWC_IO
1.8V analog ESD IO cells with low capacitor for UMC 40LP process Library_Group 40nm Contact Sales
 
 
Logic Libraries > IO Cell Library
> Analog ESD IO Library > True 3.3V Analog ESD IO Library 
Cell Name Descriptions Type Process Gradation Literature
FOH0L_PRS25_T33_ANAL
OGESD_IO
UMC 40nm LP/RVT Logic Process, 3.3V Analog ESD IO cell Library (using 2.5V overdrive 3.3V MOS) Library_Group 40nm Silver