Memory Compiler

Updated On:2018-07-24
Gradation
Faraday IPs are rated according to the IPs’ maturity and customer acceptance. They are graded by the rules described as below,


Platinum P Five (5) productions verified
Gold G Mass production proven
Silver S Silicon proven, Formal release
Silver Minus S- Manufacturing onging
Bronze B Pre-Silicon release
 
Memory Compiler > 1-Port Register File
> 6TSRAM > High Density & Low Power 1PRF, 6TSRAM 
Cell Name Descriptions Type Process Gradation Literature
FSH0L_H_SY UMC 40nm Low Power Process One Port Register File with 213 cell Memory_IP 40nm Silver Minus
 
Memory Compiler > 1-Port Register File
> 6TSRAM > High Density & Low Power 1PRF, 6TSRAM, Peri HVT 
Cell Name Descriptions Type Process Gradation Literature
FSH0L_H_SYHVT UMC 40nm low power process standard synchronous one port register file SRAM memory compiler with HVT peripheral. Memory_IP 40nm Silver Minus
 
Memory Compiler > 1-Port Register File
> 6TSRAM > High Density & Low Power 1PRF, 6TSRAM, Peri LVT 
Cell Name Descriptions Type Process Gradation Literature
FSH0L_H_SYLVT UMC 40nm low power process standard synchronous one port register file SRAM memory compiler with LVT peripheral. Memory_IP 40nm Silver Minus
 
Memory Compiler > 1-Port Register File
> 6TSRAM > High Density 1PRF, 6TSRAM 
Cell Name Descriptions Type Process Gradation Literature
FSH0L_B_SY UMC 40nm LP/HVT Logic Process with 6TSRAM (0.242 mm2) 1-port Register File Memory Compiler Memory_IP 40nm Silver
FSH0L_G_SQLVT UMC 40nm LP Logic Process Ultra High Speed One-Port Register File Memory_IP 40nm Silver
FSH0L_L_SY 40LP 1PRF with Sleep/retention/Nap mode feature Memory_IP 40nm Silver
 
Memory Compiler > 1-Port Register File
> 6TSRAM > High Density 1PRF, 6TSRAM, Peri HVT, Power Gating 
Cell Name Descriptions Type Process Gradation Literature
FSH0U_A_SYHVT UMC 40nm uLP Logic Process 1-Port Register File with Peri-HVT Memory_IP 40nm Contact Sales
 
 
Memory Compiler > 1-Port Register File
> 6TSRAM > High Density 1PRF, 6TSRAM, Peri LVT 
Cell Name Descriptions Type Process Gradation Literature
FSH0L_B_SYLVT UMC 40nm LP Logic Process single port register file memory compiler with LVT periphery Memory_IP 40nm Silver
FSH0L_L_SYLVT 40LP 1PRF with Sleep/Retention/Nap mode & peri LVT feature Memory_IP 40nm Silver
 
Memory Compiler > 1-Port Register File
> 6TSRAM > Ultra High Speed 1PRF, 6TSRAM  
Cell Name Descriptions Type Process Gradation Literature
FSH0L_D_SY UMC 40nm Low Power Process One Port Register File wit 213 cell Memory_IP 40nm Silver Minus
 
Memory Compiler > 1-Port Register File
> 6TSRAM > Ultra High Speed 1PRF, 6TSRAM, Peri HVT 
Cell Name Descriptions Type Process Gradation Literature
FSH0L_D_SYHVT UMC 40nm LP Logic Process one-port register file for area optimize with HVT peripheral Memory_IP 40nm Silver Minus
FSH0V_D_SYHVT UMC 40nm embedded high voltage (eHV) low power Process standard synchronous high density single port register file SRAM memory compiler. Memory_IP 40nm Bronze
 
Memory Compiler > 1-Port Register File
> 6TSRAM > Ultra High Speed 1PRF, 6TSRAM, Peri LVT 
Cell Name Descriptions Type Process Gradation Literature
FSH0L_D_SYLVT UMC 40nm LP Logic Process one-port register file for area optimize with LVT peripheral Memory_IP 40nm Silver Minus