Memory Compiler

Updated On:2018-07-24
Faraday IPs are rated according to the IPs’ maturity and customer acceptance. They are graded by the rules described as below,

Platinum P Five (5) productions verified
Gold G Mass production proven
Silver S Silicon proven, Formal release
Silver Minus S- Manufacturing onging
Bronze B Pre-Silicon release
Memory Compiler > 1-Port Register File
> 6TSRAM > High Density 1PRF, 6TSRAM, Peri LVT 
Cell Name Descriptions Type Process Gradation Literature
FSH0L_B_SYLVT UMC 40nm LP Logic Process single port register file memory compiler with LVT periphery Memory_IP 40nm Silver
FSH0L_L_SYLVT 40LP 1PRF with Sleep/Retention/Nap mode & peri LVT feature Memory_IP 40nm Silver