Interface Solution

Updated On:2018-07-18
Faraday IPs are rated according to the IPs’ maturity and customer acceptance. They are graded by the rules described as below,

Platinum P Five (5) productions verified
Gold G Mass production proven
Silver S Silicon proven, Formal release
Silver Minus S- Manufacturing onging
Bronze B Pre-Silicon release
Interface Solution > DDR
> DDR PHY - Combo > DDR3/3L - Combo Block 
Cell Name Descriptions Type Process Gradation Literature
FXDDR3LTA102HH0L DDR3/DDR3L/LPDDR2 combo PHY ( not support DDR3 leveling function), command / address block,UMC 40nm LP/RVT LowK Logic Process. Analog_IP 40nm Contact Sales